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參數(shù)資料
| 型號(hào)： | ST486DX2V |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 66 and 80 MHz Clock Doubled 486 CPU(66及80 MHz雙時(shí)鐘486CPU) |
| 中文描述： | 66和80 MHz時(shí)鐘倍頻486的CPU（66及80兆赫雙時(shí)鐘486CPU） |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | ST486DX2V |
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IMPROVED 486DX2 PERFORMANCE
–
Clock doubled core speeds up to 80 MHz
–
Integrated FPU 10% faster than 80486DX2
–
Up to 40 MHz bus speeds for fast local bus sys-
tems
INDUSTRY STANDARD 486 COMPATIBILITY
–
486DX socket and instruction set compatible
–
Runs DOS, Windows, OS/2, UNIX
–
Standard 168-pin PGA
–
208-pin QFP
ON-CHIP 8-KBYTE WRITE-BACK CACHE
–
Industry-wide write-back chipset support
–
Burst-mode write capability
–
Configurable as write-back or write-through
ADVANCED POWER MANAGEMENT
–
Fast SMI interrupt with separate memory space
–
Fully static design permits dynamic clock control
–
Software or hardware initiated low power sus-
pend
–
Automatic FPU power-down mode
The SGS-THOMSON ST486DX2V 3.45 volt CPUs
are advanced 486DX/DX2/DX4 compatible proc-
essors. These CPUs incorporate an on-chip
8KByte write-back cache and an integrated math
coprocessor.
The on-chip write-back cache allows up to 15%
higher performance by eliminating unnecessary
external write cycles. On traditional write-through
CPUs, these external write cycles can create bus
bottlenecks affecting system wide performance.
The integrated floating point unit, improves per-
formance up to 10% over the 80486DX2 at equal
internal frequency as measured using Power Me-
ter Whetstone test.
These processors are designed to meet the power
management requirements in the newest genera-
tion of low-power desktops and notebooks. Power
is saved by taking advantage of advanced power
management features such as static circuitry,
SMM, and automatic FPU power-down. Fast entry
and exit of SMM allows frequent use of the SMM
feature without noticeable performance degrada-
tion.
This CPU family maintains compatibility with the
installed base of x86 software and provides essen-
tial socket compatibility with the 486DX/DX2/DX4.
Decoder
Microcode ROM
Address
Sequencer
16-byte
Instruction
Execution Unit
3-Input
Adder
Limit
Unit
Multiplier
Unit
Shift
Unit
Unit
Register
File
Data
Bus
Byte
Muxes
Regs
Memory
Management
Unit
Prefetch
Unit
8 KByte
Instr/Data
Cache
Linear Address Bus
Memory
Instruction Address Bus
Data Address Bus
Address
Buffers
Bus
Control
Buffers
Data
Control
Branch Control
Control
Immediate
Control
Immediate
D31-D0
A31-A2
BE3#-BE0#
Queue
32
Execution Pipeline
8 Write
Buffers
32
Prefetch
Data Bus
1738600
SUSP#
SUSPA#
CLK
SMI#
SMADS#
FPU
Cache and Memory
Management
486DX Compatible
Bus Interface
SMM,
Suspend
Mode
and
Clock
Control
Core
Clock
Control
1/18
66 and 80 MHz clock doubled 486 CPU
ST486DX2V
October 1995
PRELIMINARY DATA
This is preliminary information on a new product undergoing evaluation. Details are subject to change without notice.
BLOCK DIAGRAM
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| ST486DX4V | 75, 100 & 120 MHz Clock Tripled 3.45 Volt 486 CPU(75, 100及120 MHz三時(shí)鐘3.45 V 486 CPU) |
| ST491AB | MAX II CPLD 2210 LE 324-FBGA |
| ST491ABD | IC SW OFFLINE 68W/117W TO262-7 |
| ST491ABDR | LOW POWER HIGH SPEED RS-485/RS-422 TRANSCEIVER |
| ST491ABN | LOW POWER HIGH SPEED RS-485/RS-422 TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ST486DX2-V50GS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST486DX2-V50QS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST486DX2-V66GS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST486DX2V66HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST486DX2V66LS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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