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參數(shù)資料
| 型號： | ST413 |
| 英文描述： | IC ACEX 1K FPGA 50K 208-PQFP |
| 中文描述： | 振蕩器| ACMOS |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 254K |
| 代理商： | ST413 |
All specifications are subject to change without notice.
SaRonix
Crystal Clock Oscillator
Technical Data
ST41xx Series
SaRonix
3.3 & 5V, ACMOS, LVCMOS
DS-183 REV C
141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
Package Details
5.08
.200
(4) Glass
Insulators
Pin 1
Tri-State
Control
FULL SIZE PACKAGE
21.0
.825
max
max
Pin 7
GND
13.0
.510
max
SARONIX
XTAL OSC
0.91
.036
max
.46±.076
.018±.003
15.24±.13
.600±.005
7.75
.305
Pin 14
VDC
Pin 8
Output
Denotes Pin 1
Tri-State Logic Table
Test Circuits
Output Waveform
Pin 1 Input
Logic 1 or NC
Logic 0 or GND
Pin 8 (5) Output
Oscillation
High Impedance
Required Input Levels on Pin 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
HALF SIZE PACKAGE
Standard Marking Format
**
Includes Date Code, Frequency, Part Number
13.0
0.91
Denotes Pin 1
5.08
.46±.08
.018±.003
7.62±.20
.300±.008
120°
120°
120°
1.5
.059
Pin 4
GND
Pin 1
Tri-State
13.0
.510
max
Pin 5
Output
Pin 8
V
DD
7.62±.20
.300±.008
Glass
Insulators
SARONIX
Standard Marking Format
**
Includes Date Code, Frequency, Part Number
Scale: None (Dimensions in inches
**
Exact location of items may vary
6.35±.51
.250±.020
6.35±.51
.250±.020
2.5 VDC
1.5 VDC
0.5 VDC
T
f
T
f
T
r
T
r
CMOS
TTL
SYMMETRY
SYMMETRY
GND
V
DD
LOGIC 0
20% V
DD
50% V
DD
80% V
DD
LOGIC 1
max
mA
M
POWER
SUPPLY
V M
V
CC
OSCILLATOR
Pad 3
Pad 2
.01 μF
OUT
GND
0.01 μF
50
TRI-STATE INPUT
(current limited on fixture)
ACMOS
50
Load
mA
M
POWER
SUPPLY
V M
ACMOS
95
Load
0.01 μF
95
TEST
POINT
V
CC
OSCILLATOR
Pad 3
Pad 2
OUT
GND
.01 μF
TRI-STATE INPUT
(current limited on fixture)
Pad 4
Pad 1
Pad 4
Pad 1
50
ACMOS TEST CIRCUIT
95
ACMOS TEST CIRCUIT
TEST
POINT
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