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ST40RA166
5 Clock generation
Power down is initiated with the sleep instruction and the power down mode is selected with bit 7 of
the CPG.STBCR register. If the bit is set, the CPU enters standby mode on the next sleep instruction,
and if unset it enters sleep mode.
5.5.2
Module low-power modes
Modules are powered down in two ways, depending on whether the module is a ST40 legacy
peripheral (controlled by the CPG register bank) or a ST40RA166 peripheral (controlled by the
CLOCKGEN
register banks).
A module controlled by the CPG register bank has its clock stopped when the corresponding bit in
the CPG.STBCR or CPG.STBCR2 register is set. The clock is started again when the bit is cleared.
To request the power down of a module controlled by the CLOCKGENA or CLOCKGENB register bank, 1
is written to the corresponding bit in the STBREQCR_SET register. When the module has completed
its power down sequence and its clock has been stopped, the corresponding bit in the STBACKCR
register is set. To restart the module, 1 is written to the corresponding bit in the STBREQCR_CLR
register.
Note:
The modules governed by the CLOCKGENB register bank do not support hardware-only power down
and require software interaction to maintain data coherency before making a request to stop the
module clock.
5.6
Clock generation registers
5.6.1
CLOCKGENB.CLK_SELCR register
CLOCKGENB.CLK_SELCR
Clock source selection
0x0068
The CLKGENB.CLK_SELCR register controls the selection of clock domain clock sources
0
LMI_SEL
Reserved
Reset state: 0
1
PCI_SEL
Select PCI clock
0: PCI_SS_CLK from CLOCKGENA_12
1: PCI_SS_CLK from CLOCKGENA_13
Reset state: 0
RW
[2:3]
EMI_SEL
Select EMI clock
00: EMI_SS_CLK from CLOCKGENA_12
01: EMI_SS_CLK from CLOCKGENA_13
10: EMI_SS_CLK from CLOCKGENA_14
11: EMI_SS_CLK from CLOCKGENB_12
Reset state: 00
RW
[4:7]
EXT_CLK_SEL
Not used
Reset state: 0000
[8:31]
Reserved
Reset state: 0
RW