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參數資料
| 型號： | ST25W02 |
| 英文描述： | Cyclone FPGA 6K TQFP-144 |
| 中文描述： | 串行2K（256 × 8）的EEPROM |
| 文件頁數： | 4/16頁 |
| 文件大小： | 145K |
| 代理商： | ST25W02 |
AI01100
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
200
300
400
0
4
8
12
16
20
CBUS (pF)
R
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x02 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x02 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing.
To start communication be-
tween the bus master and the slave ST24/25x02,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
SIGNAL DESCRIPTIONS
(cont’d)
4/16
ST24/25C02, ST24C02R, ST24/25W02
相關PDF資料 |
PDF描述 |
|---|---|
| ST25W02B1 | Cyclone FPGA 6K TQFP-144 |
| ST25W02B3 | Cyclone FPGA 6K TQFP-144 |
| ST25C02 | IC FLEX 6000 FPGA 10K 100-TQFP |
| ST25C02B1 | IC FLEX 10KE FPGA 50K 240-PQFP |
| ST25C02B3 | IC FLEX 10KE FPGA 50K 240-PQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ST25W02B1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST25W02B1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM |
| ST25W02B3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST25W02B3TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM |
| ST25W02B5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM |
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