參數(shù)資料
型號： ST25C16B6TR
廠商： 意法半導體
元件分類： DRAM
英文描述： 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
中文描述： 16千位串行I2C總線的EEPROM與用戶定義的塊寫保護
文件頁數(shù)： 10/17頁
文件大?。?/td> 126K
代理商： ST25C16B6TR
Page Write.
For the Page Write mode, the MODE
pin must be at V
IL
. The Page Write mode allows up
to 16 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the same Block Address bits
(b3, b2, b1 of Device Select code in Table 3) and
the same 4 MSBs in the Byte Address. The master
sends one up to 16 bytes of data, which are each
acknowledged by the memory. After each byte is
transfered, the internal byte address counter (4
Least Significant Bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad-
dress counter ’roll-over’ which could result in data
being overwritten. Note that for any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
WRITE Cycle
in Progress
AI01099B
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
First byte of instruction
with RW = 0 already
decoded by ST24xxx
Figure 8. Write Cycle Polling using ACK
Minimizing System Delay by Polling On ACK.
During the internal Write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the Write time (t
W
) is given in the
AC Characteristics table, this timing value may be
reduced by an ACK polling sequence issued by the
master.
The sequence is:
– Initial condition: a Write is in progress (see Fig-
ure 8).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
– Step 2: if the memory is internally writing, no
ACK will be returned. The Master goes back
to Step1. If the memory has terminated the in-
ternal writing, it will issue an ACK indicating
that the memory is ready to receive the sec-
ond part of the instruction (the first byte of this
instruction was already sent during Step 1).
10/17
ST24/25C16, ST24/25W16
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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