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參數(shù)資料
| 型號(hào)： | ST25C08M1TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| 中文描述： | 8千位串行I2C總線的EEPROM與用戶定義的塊寫保護(hù) |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | ST25C08M1TR |
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The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I
2
C bus definition. For these memories the 4 bits
are fixed as 1010b. The following bit identifies the
specific memory on the bus. It is matched to the
chip enable signal E. Thus up to 2 x 8K memories
can be connected on the same bus giving a mem-
ory capacity total of 16 Kbits. After a START condi-
tion any memory on the bus will identify the device
code and compare the following bit to its chip
enable input E.
The 6th and 7th bits sent, select the block number
(one block = 256 bytes). The 8th bit sent is the read
or write bit (RW), this bit is set to ’1’ for read and ’0’
for write operations. If a match is found, the corre-
sponding memory will acknowledge the identifica-
tion on the SDA bus during the 9th bit time.
Input Rise and Fall Times
≤
50ns
Input Pulse Voltages
0.2V
CC
to 0.8V
CC
Input and Output Timing Ref.
Voltages
0.3V
CC
to 0.7V
CC
Table 8. AC Measurement Conditions
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure 4. AC Testing Input Output Waveforms
DEVICE OPERATION
(cont’d)
Symbol
Alt
Parameter
Min
Max
Unit
t
CH1CH2
t
R
Clock Rise Time
1
μ
s
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2
t
R
Input Rise Time
1
μ
s
t
DL1DL1
t
F
Input Fall Time
300
ns
t
CHDX (1)
t
SU:STA
Clock High to Input Transition
4.7
μ
s
t
CHCL
t
HIGH
Clock Pulse Width High
4
μ
s
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
4
μ
s
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
μ
s
t
CLCH
t
LOW
Clock Pulse Width Low
4.7
μ
s
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
250
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
4.7
μ
s
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
4.7
μ
s
t
CLQV (2)
t
AA
Clock Low to Next Data Out Valid
0.3
3.5
μ
s
t
CLQX
t
DH
Data Out Hold Time
300
ns
f
C
f
SCL
Clock Frequency
100
kHz
t
W (3)
t
WR
Write Time
10
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C; V
CC
= 3V to 5.5V or 2.5V to 5.5V)
6/16
ST24/25C08, ST24/25W08
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