參數(shù)資料
型號： ST25C08B1TR
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
中文描述： 8千位串行I2C總線的EEPROM與用戶定義的塊寫保護(hù)
文件頁數(shù)： 12/16頁
文件大?。?/td> 125K
代理商： ST25C08B1TR
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode.
In all read modes
the ST24/25x08 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x08 terminate the
data transfer and switches to a standby state.
S
DEV SEL *
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI00794C
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
Figure 11. Read Modes Sequence
Note:
* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
DEVICE OPERATION
(cont’d)
12/16
ST24/25C08, ST24/25W08
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