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參數(shù)資料
| 型號(hào)： | ST24W16M6TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| 中文描述： | 16千位串行I2C總線的EEPROM與用戶定義的塊寫保護(hù) |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 126K |
| 代理商： | ST24W16M6TR |
Symbol
Alt
Parameter
Min
Max
Unit
t
CH1CH2
t
R
Clock Rise Time
1
μ
s
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2
t
R
Input Rise Time
1
μ
s
t
DL1DL1
t
F
Input Fall Time
300
ns
t
CHDX
(1)
t
SU:STA
Clock High to Input Transition
4.7
μ
s
t
CHCL
t
HIGH
Clock Pulse Width High
4
μ
s
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
4
μ
s
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
μ
s
t
CLCH
t
LOW
Clock Pulse Width Low
4.7
μ
s
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
250
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
4.7
μ
s
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
4.7
μ
s
t
CLQV (2)
t
AA
Clock Low to Next Data Out Valid
0.3
3.5
μ
s
t
CLQX
t
DH
Data Out Hold Time
300
ns
f
C
f
SCL
Clock Frequency
100
kHz
t
W
(3)
t
WR
Write Time
10
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)
the maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(T
A
= 0 to 70
°
C or –40 to 85
°
C; V
CC
= 4.5V to 5.5V or 2.5V to 5.5V)
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x16 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure 4. AC Testing Input Output Waveforms
Input Rise and Fall Times
≤
50ns
Input Pulse Voltages
0.2V
CC
to 0.8V
CC
Input and Output Timing Ref.
Voltages
0.3V
CC
to 0.7V
CC
Table 8. AC Measurement Conditions
6/17
ST24/25C16, ST24/25W16
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