參數(shù)資料
型號: ST24W08M3TR
廠商: 意法半導體
元件分類: DRAM
英文描述: 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
中文描述: 8千位串行I2C總線的EEPROM與用戶定義的塊寫保護
文件頁數(shù): 9/16頁
文件大?。?/td> 125K
代理商: ST24W08M3TR
AI01121B
3FFh
b7
b2
X
X
300h
Block 3
Block 0
Protect Flag
Enable = 0
Disable = 1
Page
pointer
b4
0
Figure 7. Memory Protection
of data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte
address counter (4 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master.
WRITE Cycle
in Progress
AI01099B
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
First byte of instruction
with RW = 0 already
decoded by ST24xxx
Figure 8. Write Cycle Polling using ACK
9/16
ST24/25C08, ST24/25W08
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