參數(shù)資料
型號(hào)： ST24W02B1
廠商： 意法半導(dǎo)體
英文描述： Cyclone II FPGA 50K FBGA-672
中文描述： I2C串行EEPROM的
文件頁(yè)數(shù)： 6/16頁(yè)
文件大小： 145K
代理商： ST24W02B1
Symbol
Alt
Parameter
Min
Max
Unit
t
CH1CH2
t
R
Clock Rise Time
1
μ
s
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2
t
R
Input Rise Time
1
μ
s
t
DL1DL1
t
F
Input Fall Time
300
ns
t
CHDX (1)
t
SU:STA
Clock High to Input Transition
4.7
μ
s
t
CHCL
t
HIGH
Clock Pulse Width High
4
μ
s
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
4
μ
s
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
μ
s
t
CLCH
t
LOW
Clock Pulse Width Low
4.7
μ
s
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
250
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
4.7
μ
s
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
4.7
μ
s
t
CLQV (2)
t
AA
Clock Low to Next Data Out Valid
0.3
3.5
μ
s
t
CLQX
t
DH
Data Out Hold Time
300
ns
f
C
f
SCL
Clock Frequency
100
kHz
t
W (3)
t
WR
Write Time
10
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C; V
CC
= 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I
2
C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
Input Rise and Fall Times
≤
50ns
Input Pulse Voltages
0.2V
CC
to 0.8V
CC
Input and Output Timing Ref. Voltages 0.3V
CC
to 0.7V
CC
AC MEASUREMENT CONDITIONS
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure 4. AC Testing Input Output Waveforms
DEVICE OPERATION
(cont’d)
6/16
ST24/25C02, ST24C02R, ST24/25W02
相關(guān)PDF資料
PDF描述
ST24W02B3 Cyclone II FPGA 5K FBGA-256
ST24W02B6 Cyclone II FPGA 70K FBGA-896
ST24W02M1 Cyclone II FPGA 5K TQFP-144
ST24W02M3 FPGA, FLEX 10K, 20K GATES, TQFP144; Logic IC family:FPGA; Logic IC Base Number:10; Logic IC function:EPF10K20; Voltage, supply:5.0V; Case style:TQFP; Gates, No. of:20000; I/O lines, No. of:102; Pins, No. of:144; Temp, op. RoHS Compliant: Yes
ST24W02M6 CPLD. MAX 7000, 160 MACROCELLS, TQFP100; Logic IC family:CPLD (EPLD); Logic IC Base Number:7160; Logic IC function:EPM7160S; Voltage, supply:5V; Case style:TQFP; Gates, No. of:3200; I/O lines, No. of:84; Macrocells, No. of:160; Pins, RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST24W02B1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM
ST24W02B3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM
ST24W02B3TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM
ST24W02B5TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM
ST24W02B6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM
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