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參數(shù)資料
| 型號： | ST24LW21M6 |
| 英文描述： | Cyclone II FPGA 15K FBGA-256 |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 152K |
| 代理商： | ST24LW21M6 |
Symbol
Alt
Parameter
Min
Max
Unit
t
CH1CH2
(1)
t
R
Clock Rise Time
300
ns
t
CL1CL2
(1)
t
F
Clock Fall Time
300
ns
t
DH1DH2
(1)
t
R
SDA Rise Time
20
300
ns
t
DL1DL2
(1)
t
F
SDA Fall Time
20
300
ns
t
CHDX
(2)
t
SU:STA
Clock High to Input Transition
600
ns
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
600
ns
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
μ
s
t
CLCH
t
LOW
Clock Pulse Width Low
1.3
μ
s
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
100
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
600
ns
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
1.3
μ
s
t
CLQV
t
AA
Clock Low to Data Out Valid
200
900
ns
t
CLQX
t
DH
Clock Low to Data Out Transition
200
ns
f
C
f
SCL
Clock Frequency
400
kHz
t
W
t
WR
Write Time
10
ms
Notes:
1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
Table 7. AC Characteristics, I
2
C Bidirectional Mode for Clock Frequency = 400kHz
(T
A
= –40 to 85
°
C; V
CC
= 3.6V to 5.5V)
DEVICE OPERATION
I
2
C Bus Background
The ST24xy21 supports the I
2
C protocol. This pro-
tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24xy21 are always slave de-
vices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input, the ST24xy21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.
9/21
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24LW21M6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
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| ST24T3H 032397 | 制造商:Comair Rotron 功能描述:FAN 80MM 24VDC |
| ST24T3H | 制造商:Comair Rotron 功能描述:FAN 80MM 24VDC |
| ST24W01 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 1K 128 x 8 EEPROM |
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