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參數(shù)資料
| 型號： | ST24FC21BB1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| 中文描述： | 1千位x8雙模式串行EEPROM的韋莎插頭 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 159K |
| 代理商： | ST24FC21BB1TR |
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write.
The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK
.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
– Initial condition: a Write is in progress (see Fig-
ure 10).
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
AI01893
S
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
VCLK/WC
VCLK/WC
Figure 11. Write Modes Sequence
15/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST24LC21BB6TR | ECONOLINE: REC5-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 5W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| ST24FC21BB6TR | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21B1TR | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21B6TR | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21M1TR | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24FC21BB6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21BM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21BM6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FC21M1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST24FC21M1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
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