參數(shù)資料
型號(hào): ST24C16B1TR
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
中文描述: 16千位串行I2C總線的EEPROM與用戶定義的塊寫保護(hù)
文件頁(yè)數(shù): 3/17頁(yè)
文件大小: 126K
代理商: ST24C16B1TR
Mode
RW bit
MODE pin
Bytes
Initial Sequence
Current Address Read
’1’
X
1
START, Device Select, RW = ’1’
Random Address Read
’0’
X
1
START, Device Select, RW = ’0’, Address,
’1’
reSTART, Device Select, RW = ’1’
Sequential Read
’1’
X
1 to 2048
As CURRENT or RANDOM Mode
Byte Write
’0’
X
1
START, Device Select, RW = ’0’
Multibyte Write
’0’
V
IH
8
START, Device Select, RW = ’0’
Page Write
’0’
V
IL
16
START, Device Select, RW = ’0’
Note:
X = V
IH
or V
IL
.
Table 4. Operating Modes
Device Code
Memory MSB Addresses
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
A10
A9
A8
RW
Note:
The MSB b7 is sent first.
Table 3. Device Select Code
memory it responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow-
ledges the receipt of the data bytes in the same
way. Data transfers are terminated with a STOP
condition.
Data in the 4 upper blocks of the memory may be
write protected. The protected area is programma-
ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven
High.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
CC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
3/17
ST24/25C16, ST24/25W16
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