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參數(shù)資料
| 型號： | ST24C08M5 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Stratix II FPGA 180K FBGA-1508 |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 125K |
| 代理商： | ST24C08M5 |
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01161B
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
NO ACK
R/W
ACK
ACK
NO ACK
R/W
NO ACK
NO ACK
Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W08)
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read.
The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
Random Address Read.
A dummy write is per-
formed to load the address into the address counter
(see Figure 11). This is followed by another START
condition from the master and the byte address is
repeated with the RW bit set to ’1’. The memory
acknowledges this and outputs the byte ad-
dressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
Sequential Read.
This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
11/16
ST24/25C08, ST24/25W08
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST24C08M6 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST24W08M6 | Cyclone II FPGA 20K FBGA-256 |
| ST24C08 | 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| ST24C08B1TR | 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| ST24C08B3TR | 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24C08M5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| ST24C08M6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM |
| ST24C08M6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| ST24C08RB1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST24C08RB3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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