參數(shù)資料
型號: ST24C08M3
廠商: 意法半導體
英文描述: Cyclone II FPGA 35K FBGA-484
中文描述: I2C串行EEPROM的
文件頁數(shù): 8/16頁
文件大小: 125K
代理商: ST24C08M3
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Figure 6. I
2
C Bus Protocol
Multibyte Write.
For the Multibyte Write mode, the
MODE pin must be at V
IH
. The Multibyte Write
mode can be started from any address in the
memory. The master sends from one up to 8 bytes
of data, which are each acknowledged by the mem-
ory. The transfer is terminated by the master gen-
erating a STOP condition. The duration of the write
cycle is t
W
= 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 5 most significant address bits A7-
A3), the programming time is then doubled to a
maximum of 20ms. Writing more than 8 bytes in the
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 16 bytes long). However,
the Multibyte Write can properly write up to 16
consecutive bytes only if the first address of these
16 bytes is the first address of the row, the 15
following bytes being written in the 15 following
bytes of this same row.
Page Write.
For the Page Write mode the MODE
pin must be at V
IL
. The Page Write mode allows up
to 16 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the 4 most significant mem-
ory address bits (A7-A4) are the same inside one
block. The master sends from one up to 16 bytes
8/16
ST24/25C08, ST24/25W08
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