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參數(shù)資料
| 型號(hào)： | ST24C02RM5TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SERIAL 2K (256 x 8) EEPROM |
| 中文描述： | 串行2K（256 × 8）的EEPROM |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 145K |
| 代理商： | ST24C02RM5TR |
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Figure 6. I
2
C Bus Protocol
Write Operations
The Multibyte Write mode (only available on the
ST24/25C02 and ST24C02R versions) is selected
when the MODE pin is at V
IH
and the Page Write
mode when MODE pin is at V
IL
. The MODE pin may
be driven dynamically with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac-
cess to 256 bytes of the memory. After receipt of
the byte address the device again responds with
an acknowledge.
For the ST24/25W02 versions, any write command
with WC = 1 will not modify the memory content.
Byte Write.
In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either V
IH
or V
IL
, to minimize the stand-by current.
8/16
ST24/25C02, ST24C02R, ST24/25W02
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