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參數資料
| 型號： | ST24C02M1TR |
| 廠商： | 意法半導體 |
| 英文描述： | SERIAL 2K (256 x 8) EEPROM |
| 中文描述： | 串行2K（256 × 8）的EEPROM |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 145K |
| 代理商： | ST24C02M1TR |
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01101B
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W02)
Sequential Read.
This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode.
In all read modes
the ST24/25x02 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x02 terminate the
data transfer and switches to a standby state.
11/16
ST24/25C02, ST24C02R, ST24/25W02
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