參數(shù)資料
型號： ST16C580CQ48-F
廠商： Exar Corporation
文件頁數(shù)： 11/39頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B 48TQFP
標準包裝： 250
特點： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應商設備封裝： 48-TQFP（7x7）
包裝： 托盤
ST16C580
19
Rev. 1.22
logic 0. Once active the -TXRDY pin will go to a logic 1
after the first character is loaded into the transmit
holding register.
Receive operation in mode “0”:
When the 580 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the 580 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Receive operation in mode “1”:
When the 580 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = 1)
These bits are used to set the trigger level for the
transmit FIFO interrupt. The ST16C580 will issue a
transmit empty interrupt when the number of charac-
ters in FIFO drops below the selected trigger level.
BIT-5
BIT-4
TX FIFO trigger level
00
1
01
4
10
8
11
14
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level =8)
These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters
in the FIFO equals the programmed trigger level. How-
ever the FIFO will continue to be loaded until it is full.
BIT-7
BIT-6
RX FIFO trigger level
00
1
01
4
10
8
11
14
Interrupt Status Register (ISR)
The 580 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
rupt status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. When-
ever the interrupt status register is read, the interrupt
status is cleared. However it should be noted that only
the current pending interrupt is cleared by the read. A
lower level interrupt may be seen after rereading the
interrupt status bits. The Interrupt Source Table 6
(below) shows the data values (bit 0-5) for the six
prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels:
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