參數(shù)資料
型號: ST16C552CJ68TR-F
廠商: Exar Corporation
文件頁數(shù): 17/39頁
文件大小: 0K
描述: IC UART FIFO 16B DUAL 68PLCC
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: 打印機
電源電壓: 2.97 V ~ 5.5 V
帶并行端口:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 帶卷 (TR)
其它名稱: ST16C552CJ68TR-F-ND
24
ST16C552/552A
Rev. 3.40
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to MCR bit-2 in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to MCR bit-3 in the MCR register.
Note: Whenever any MSR bit 0-3: is set to logic “1”, a
MODEM Status Interrupt will be generated.
Scratchpad Register (SPR)
The ST16C552/552A provides a temporary data reg-
ister to store 8 bits of user information.
PRINTER PORT REGISTER DESCRIPTIONS
Port Register (PR)
PR BIT 0-7:
Printer Data port (Bi-directional) - These pins are the
eight bit data bus for transferring information to or
from an external device (usually a printer). D0 is the
least significant bit. PD7-PD0 are latched during a
write cycle (output mode).
I/O Select Register (IOSEL)
This bit is used in conjunction with the state of BIDEN
to set the direction (input/output) of the PD7-PD0 data
bus. This register is used only when BIDEN is a logic
0.
Logic 55 (Hex) + BIDEN 0 = PD7-PD0 are set for
output mode
Logic AA (Hex) + BIDEN 0 = PD7-PD0 are set for input
mode
Status Register (SR)
This register provides the printer port input logical
states and the status of the interrupt -INTP based on
the condition of the -ACK printer port interface signal.
The logical state of these pins is dependent on exter-
nal interface signals.
SR BIT 1-0:
Not Used - initialized to a logic 1.
SR BIT-2:
Logic 0 = an interrupt is pending
When INTSEL is a logic 0, SR bit-2 basically tracks the
-ACK input interface pin (returns to a logic 1 when the
-ACK input returns to a logic 1). However when
INTSEL is a logic 1, the latched mode is selected, SR
bit-2 goes to a logic 0 with the -ACK input but does not
return to a logic 1 until the end of the read cycle, i.e.,
reading SR will set this bit to a logic 1.
Logic 1 = no interrupt is pending. (normal inactive
state)
SR BIT-3:
Logic 0 = -ERROR input is a logic 0.
Logic 1 = -ERROR input is a logic 1. (normal inactive
state)
SR BIT-4:
Logic 0 = SLCT input is a logic 0. (normal inactive
state)
Logic 1 = SLCT input is a logic 1.
SR BIT-5:
Logic 0 = PE input is a logic 0. (normal inactive state)
Logic 1 = PE input is a logic 1.
SR BIT-6:
Logic 0 = -ACK input is a logic 0.
Logic 1 = -ACK input is a logic 1. (normal inactive
state)
SR BIT-7:
Logic 0 = BUSY input is a logic 0
Logic 1 = BUSY input is a logic 1 (normal inactive
state)
Command Register (COM)
This register provides the printer port input logical
states and the status of the printer interrupt INIT,
which is based on the state of CON bit-1.
COM BIT-0:
-STROBE is a bi-directional signal with an open
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