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參數(shù)資料
| 型號： | ST16C552AIJ68-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B DUAL 68PLCC |
| 標準包裝： | 19 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | 打印機 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC |
| 包裝： | 管件 |
| 其它名稱： | 1016-1566-5 1016-1566-5-ND 1016-1665 ST16C552AIJ68-F-ND |
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20
ST16C552/552A
Rev. 3.40
FCR BIT 4-5:
Not Used - initialized to a logic 0.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
BIT-6
RX FIFO trigger level
0
01
0
1
04
1
0
08
1
14
Interrupt Status Register (ISR)
The 552/552A provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
four interrupt status bits. Performing a read cycle on
the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are
acknowledged until the pending interrupt is serviced.
Whenever the interrupt status register is read, the
interrupt status is cleared. However it should be noted
that only the current pending interrupt is cleared by the
read. A lower level interrupt may be seen after reread-
ing the interrupt status bits. The Interrupt Source
Table 8 (below) shows the data values (bits 0-3) for the
four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
Table 8, INTERRUPT SOURCE TABLE
Priority
[ISR BITS]
Level
Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
2
1
0
RXRDY (Receive Data time out)
3
0
1
0
TXRDY (Transmitter Holding Register Empty)
4
0
MSR (Modem Status Register)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C552CJ | 制造商:STARTECH 功能描述: |
| ST16C552CJ68 | 制造商:Rochester Electronics LLC 功能描述:DUAL PORT 16 BYTE FIFO AND PARALLEL PRINTR - Bulk 制造商:Exar Corporation 功能描述: |
| ST16C552CJ68-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C552CJ68TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C552IJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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