參數資料
型號: ST16C452CJ68-F
廠商: Exar Corporation
文件頁數: 30/30頁
文件大?。?/td> 0K
描述: IC UART W/PAR PORT DUAL 68PLCC
標準包裝: 19
特點: *
通道數: 2,DUART
FIFO's: 1 字節(jié)
規(guī)程: 打印機
電源電壓: 2.97 V ~ 5.5 V
帶并行端口:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應商設備封裝: 68-PLCC
包裝: 管件
其它名稱: ST16C452CJ68-F-ND
9
ST16C452/452PS
Rev. 3.20
Table 4, INTERNAL REGISTER DECODE
A2
A1
A0
READMODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
1
0
Modem Status Register
1
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3
X
0
PORT REGISTER
X
0
1
STATUS REGISTER
I/O SELECT REGISTER
X
1
0
COMMAND REGISTER
CONTROL REGISTER
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.
Programmable Baud Rate Generator
The 452/452PS supports high speed modem technolo-
gies that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input data
rate of 460.8Kbps. The 452/452PS can support a
standard data rate of 921.6Kbps.
Single baud rate generator is provided for the transmitter
and receiver, allowing independent TX/RX channel con-
trol. The programmable Baud Rate Generator is capable
of accepting an input clock up to 24 MHz, as required
for supporting a 1.5Mbps data rate. The 452/452PS
requires that an external clock source be connected to
the CLK input pin to clock the internal baud rate
generator for standard or custom rates. (see Baud Rate
Generator Programming below).
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