REV. 4.0.1 16 LCR[7]: Baud Rate Divisors (DLL/DLM) Enable Logic 0 = D" />
參數(shù)資料
型號: ST16C2450IJ44-F
廠商: Exar Corporation
文件頁數(shù): 8/30頁
文件大?。?/td> 0K
描述: IC UART FIFO DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié)
規(guī)程: RS232
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
ST16C2450
xr
2.97V TO 5.5V DUART
REV. 4.0.1
16
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.6
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2450. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 7.
MCR[7:5]: Reserved
4.7
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register .
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error. An interrupt will be
generated immediately if LSR interrupt is enabled (IER bit-2).
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