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參數(shù)資料
| 型號(hào)： | ST10R172LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 53/68頁(yè) |
| 文件大?。?/td> | 657K |
| 代理商： | ST10R172LT6 |
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.5 CLKOUT and READY/READY
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40°C to +85 °C
CL = 50 pF
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
Un
it
min.
max.
min.
max.
CLKOUT cycle time
t29 CC 20
20
2TCL
ns
CLKOUT high time
t30 CC 5
–
TCL – 5
–
ns
CLKOUT low time
t31 CC 5
–
TCL – 5
–
ns
CLKOUT rise time1)
1) Measured between 0.3 and 2.7 volts
t32 CC –
31
–
31
ns
CLKOUT fall time1
t33 CC –
31
–
31
ns
CLKOUT rising edge to
ALE falling edge
t34 CC -3 + tA
5 +
tA
-3 +
tA
5 +
tA
ns
Synchronous READY
setup time to CLKOUT
t35 SR 9
–
9
–
ns
Synchronous READY
hold time after CLKOUT
t36 SR 0
–
0
–
ns
Asynchronous READY
low time
t37 SR 27
–
2TCL + 7
–
ns
Asynchronous READY
setup time2)
2) These timings assure recognition at a specific clock edge for test purposes only.
t58 SR 9
–
9
–
ns
Asynchronous READY
hold time2
t59 SR 0
–
0
–
ns
Async. READY hold time
after RD, WR high (Demulti-
plexed Bus)3)2
3) Demultiplexed bus is the worst case. For multiplexed bus, 2TCL should be added
to the maximum values. This adds even more time for deactivating READY.
2tA and tC refer to the following bus cycle, tF refers to the current bus cycle.
t60 SR 0
0
+ 2
tA+ tc+ tF
3
0TCL - 10
+ 2
tA+ tc+ tF
3
ns
Table16CLKOUT and READY/READY
1
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