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參數(shù)資料
| 型號(hào)： | SSTV16857MTDX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 85K |
| 代理商： | SSTV16857MTDX |
2005 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
September 2000
Revised June 2005
SSTV168
57
SSTVN16857
14-Bi
tRegist
er
wit
h
SSTL-
2
C
o
m
p
ati
b
le
I/O
and
Rese
t
SSTV16857 SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications.
The
SSTVN16857
is
a
14-bit
register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
s Compliant with DDR-I registered module specifications
s Operates at 2.5V
r 0.2V VDD
s SSTL-2 compatible input and output structure
s Differential SSTL-2 compatible clock inputs
s Low power mode when device is reset
s Industry standard 48 pin TSSOP package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Truth Table
L
Logic LOW
H
Logic HIGH
X
Don’t Care, but not floating unless noted
n LOW-to-HIGH Clock Transition
p HIGH-to-LOW Clock Transition
Order Number
Package Number
Package Description
SSTV16857MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
SSTVN16857MTD
(Preliminary)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Name
Description
Q1-Q14
SSTL-2 Compatible Output
D1-D14
SSTL-2 Compatible Inputs
RESET
Asynchronous LVCMOS Reset Input
CK
Positive Master Clock Input
CK
Negative Master Clock Input
VREF
Voltage Reference Pin for SSTL Level Inputs
VDDQ
Power Supply Voltage for Output Signals
VDD
Power Supply Voltage for Inputs
RESET
Dn
CK
Qn
LX or
Floating
X or
Floating
X or
Floating
L
HL
np
L
HH
np
H
HX
L
H
Qn
HX
H
L
Qn
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSTV16857MTDX_NL | |
| SSTV16857MTD_NL | |
| SSW-1-05-22-SM-S-VS | 5 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| SSW-1-05-22-STL-T-VS | 15 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| SSW-1-06-22-FM-D-VS | 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTV16857MTDX_NL | 功能描述:寄存器 14-Bit Register with SSTL-2 Compatible I/O and Reset RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16857TE-E | 制造商:Renesas Electronics Corporation 功能描述:14-BIT SSTL_2 REGISTERED BUFFER TSSOP 48 PIN - Tape and Reel |
| SSTV16859 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM |
| SSTV16859_ZAA31162 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SSTV16859_ZBA30062 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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