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參數(shù)資料
| 型號(hào)： | SSTL16857 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 14-bit SSTL_2 registered driver with differential clock inputs |
| 中文描述： | SSTL SERIES, POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, PDSO48 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | SSTL16857 |
Philips Semiconductors
Product specification
SSTL16857
14-bit SSTL_2 registered driver with
differential clock inputs
2
1999 Sep 30
853-2155 22448
FEATURES
Stub-series terminated logic for 2.5V VDDQ (SSTL_2)
Optimized for DDR (Double Data Rate) SDRAM applications
Supports SSTL_2 signal inputs and outputs
Flow-through architecture optimizes PCB layout
Meets SSTL_2 class I and class II specifications
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 833 Method 3015
and 200 V per Machine Model
Full DDR solution provided when used with PCK857 and CBT3857
DESCRIPTION
The SSTL16857 is a 14-bit SSTL_2 registered driver with differential
clock inputs. Both V
CC
and V
DDQ
support 2.5V and 3.3V operation
however. V
DDQ
must not exceed V
CC
. Inputs are SSTL_2 type with
V
REF
normally at 0.5*V
DDQ
. The outputs support class I which can
be used for standard stub-series applications or capacitive loads.
Master reset (RESET) asynchronously resets all registers to zero.
The SSTL16857 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of
200 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTL16857 is intended to be used for SSTL_2
input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VDDQ
Q5
Q6
Q9
Q10
D12
D11
D10
D9
D8
RESET
VREF
GND
VCC
CLK+
CLK–
D7
D6
D5
D4
D3
VCC
GND
D2
D1
21
22
23
24
25
26
27
28
VDDQ
Q14
D14
D13
GND
VCC
Q1
Q2
GND
Q3
Q4
GND
VDDQ
Q7
VDDQ
GND
Q8
VDDQ
GND
Q11
Q12
GND
Q13
SW00311
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
I
Propagation delay; CLK to Qn
C
L
= 30 pF; V
DDQ
= 2.5 V
V
CC
= 2.5V
1.8
ns
Input capacitance
2.9
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W) P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacity in pF; f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
V
CC2
x f
i
(C
L
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
48-Pin Plastic TSSOP Type I
0
°
C to +70
°
C
SSTL16857 DGG
SOT362-1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTL16857DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14-bit SSTL_2 registered driver with differential clock inputs |
| SSTL16857DGG,112 | 功能描述:寄存器 14-BIT SSTL 2 REG DRIVER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTL16857DGG,118 | 功能描述:寄存器 14-BIT SSTL 2 REG DRIVER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTL16877 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14-bit SSTL_2 registered driver with differential clock inputs |
| SSTL16877DG | 功能描述:寄存器 20-BIT REG DRVR W/INV REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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