參數(shù)資料
型號(hào): SST89V554RC-25-C-NJ
廠(chǎng)商: SILICON STORAGE TECHNOLOGY INC
元件分類(lèi): 微控制器/微處理器
英文描述: FlashFlex51 MCU
中文描述: 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 27/62頁(yè)
文件大?。?/td> 680K
代理商: SST89V554RC-25-C-NJ
Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
27
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using the following two methods:
External Host Mode
In-Application Programming (IAP) Mode
4.1 External Host Programming Mode
External Host Programming Mode allows the user to pro-
gram the Flash memory directly without using the CPU.
External Host Mode is entered by forcing PSEN# from a
logic high to a logic low while RST input is being held con-
tinuously high. The device will stay in External Host Mode
as long as RST = 1 and PSEN# = 0.
A Read-ID operation is necessary to “arm” the device in
External Host Mode, and no other External Host Mode com-
mands can be enabled until a Read-ID is performed. In
External Host Mode, the internal Flash memory blocks are
accessed through the re-assigned I/O port pins (see Figure
4-1 for details) by an external host, such as a MCU program-
mer, a PCB tester or a PC-controlled development board.
Note:
Symbol
signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of
the above input pins are invalid and may result in unexpected behaviors.
Note:
V
IL
= Input Low Voltage;
V
IH
= Input High Voltage;
V
IH1
= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output
TABLE
4-1: E
XTERNAL
H
OST
M
ODE
C
OMMANDS
FOR
SST89E564RD/SST89V564RD
Operation
Read-ID
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Select-Block0
Select-Block1
Prog-SC0
Prog-SB1
Prog-SB2
Prog-SB3
RST
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
PSEN#
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
PROG#/
ALE
V
IH
V
IH
EA#
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
P3[7]
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
P3[6]
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
Il
V
Il
V
IL
V
IH
V
IL
V
IH
P2[7]
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
Il
V
Il
V
IL
V
IH
V
IH
V
IL
P2[6]
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
P0[7:0]
DO
X
X
X
DI
DO
X
X
X
X
X
X
P3[5:4]
P2[5:0]
AH
X
X
AH
AH
AH
55H
A5H
5AH
X
X
X
P1[7:0]
AL
X
X
AL
AL
AL
X
X
X
X
X
X
T4-1.0 555
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