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參數(shù)資料
| 型號(hào)： | SST89E554RC-25-C-PJ |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | FlashFlex51 MCU |
| 中文描述： | FlashFlex51單片機(jī) |
| 文件頁數(shù)： | 49/62頁 |
| 文件大?。?/td> | 680K |
| 代理商： | SST89E554RC-25-C-PJ |
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Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
49
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
TABLE
10-2: P
OWER
S
AVING
M
ODES
Mode
Idle Mode
Initiated by
Software
(Set IDL bit in
PCON)
State of MCU
Exited by
CLK is running.
Interrupts, serial port and tim-
ers/counters are active. Pro-
gram Counter is stopped.
ALE and PSEN# signals at a
HIGH level during Idle. All
registers remain unchanged.
Enabled interrupt or hardware reset.
Start of interrupt clears IDL bit and
exits Idle mode, after the ISR RETI
instruction, program resumes execu-
tion beginning at the instruction follow-
ing the one that invoked Idle mode. A
user could consider placing two or
three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware
reset restarts the device similar to a
power-on reset.
Enabled external level sensitive inter-
rupt or hardware reset. Start of inter-
rupt clears PD bit and exits Power
Down mode, after the ISR RETI
instruction program resumes execution
beginning at the instruction following
the one that invoked Power Down
mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes Power Down
mode to eliminate any problems. A
hardware reset restarts the device sim-
ilar to a power-on reset.
Gate ON external clock. Program exe-
cution resumes at the instruction fol-
lowing the one during which the clock
was gated off.
Power Down
Mode
Software
(Set PD bit in
PCON)
CLK is stopped. On-chip
SRAM and SFR data is main-
tained. ALE and PSEN# sig-
nals at a LOW level during
Power Down. External Inter-
rupts are only active for level
sensitive interrupts, if
enabled.
Standby (Stop
Clock) Mode
External hardware gates OFF
the external clock input to the
MCU. This gating should be
synchronized with an input
clock transition (low-to-high or
high-to-low).
CLK is frozen. On-chip SRAM
and SFR data is maintained.
ALE and PSEN# are main-
tained at the levels prior to
the clock being frozen.
T10-2.0 555
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST89V554RC-25-C-PJ | FlashFlex51 MCU |
| SST89E554RC-25-C-TQI | FlashFlex51 MCU |
| SST89V554RC-25-C-TQI | FlashFlex51 MCU |
| SST89E554RC-25-C-TQJ | FlashFlex51 MCU |
| SST89V554RC-25-C-TQJ | FlashFlex51 MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST89E554RC-25-C-TQI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-C-TQJ | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-I-NI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-I-NJ | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-I-PI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
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