參數(shù)資料
型號(hào)： SST85LP1004B-M-C-LFTE
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝： 14 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, BGA-91
文件頁數(shù)： 35/36頁
文件大?。?/td> 910K
代理商： SST85LP1004B-M-C-LFTE
2010 Silicon Storage Technology, Inc.
S71420-01-000
04/10
8
4 GByte NANDrive
SST85LP1004B
Advance Information
IOWR#
H9
I
I2Z
IOWR#: This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into
the device. (This pin supports two functions)
STOP: When Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst
IORDY
J4
O
O2
IORDY: When in PIO mode, the device is not ready to respond to a data
transfer request. This signal is negated to extend the Host transfer cycle
from the assertion of IORD# or IOWR#. However, it is never negated by
this controller. (This pin supports three functions)
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal is
asserted by the device to indicate that the device is ready to receive
Ultra DMA data-out bursts. The device may negate DDMARDY# to
pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-in strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-in
burst.
IOCS16#
J8
O
O3
This output signal is asserted low when the device is indicating a word
data transfer cycle.
INTRQ
J2
O
O2
This signal is the active high Interrupt Request to the host.
PDIAG#
K9
I/O
I1U/O2 The Pass Diagnostic signal in the Master/Slave handshake protocol.
DASP#
D9
I/O
I1U/O4 The Drive Active/Slave Present signal in the Master/Slave handshake
protocol.
RESET#
E4
I
I2U
This input pin is the active low hardware reset from the host.
Serial Communication Interface (SCI)
SCIDOUT
D8
O
O2
SCI interface data output
SCIDIN
D7
I
I1U
SCI interface data input
SCICLK
E7
I
I1D
SCI interface clock
Miscellaneous
WP#/PD#
F6
I
I2U
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The Write
Protect or Power-down modes can be selected through the host com-
mand. The Write Protect mode is the factory default setting.
VSS1
G4, G6, G7,
K4, K6, K7,
J9
PWR
Ground
VDD1
E2, E9, K5,
L5, M2, M9
PWR
VDD (3.3V)
Table 1: Pin Assignments (Continued) (2 of 3)
Symbol
Pin No.
Pin
Type
I/O
Type
Name and Functions
91-LBGA
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