參數(shù)資料
型號: SST85LD0512-60-RI-LBTE
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝: 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91
文件頁數(shù): 4/36頁
文件大小: 913K
代理商: SST85LD0512-60-RI-LBTE
2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
12
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Power-on and Brown-out Reset Characteristics
Please contact SST to obtain NANDrive reference design schematics including the POR# circuit for
industrial NANDrive offerings.
Figure 3: Power-on and Brown-out Reset Timing
I/O Transfer Function
The default operation for the NANDrive is 16-bit. However, if the host issues a Set-Feature command
to enable 8-bit mode, the NANDrive permits 8-bit data access.
The following table defines the function of various operations.
Table 6: Power-on and Brown-out Reset Timing
Item
Symbol
Min
Max
Units
VDD/POR# Rise Time1
1. VDD Rise Time should be faster than or equal to POR# Rise Time.
TR
250
ms
VDD/POR# Fall Time2
2. VDD Fall Time should be slower than or equal to POR# Fall Time.
TF
250
ms
T6.0 1382
Table 7: I/O Function
Function Code
CS3FX#
CS1FX#
A0-A2
IORD#
IOWR#
D15-D8
D7-D0
Invalid Mode
VIL
X
Undefined
Standby Mode
VIH
X
High Z
Task File Write
VIH
VIL
1-7H
VIH
VIL
X
Data In
Task File Read
VIH
VIL
1-7H
VIL
VIH
High Z
Data Out
Data Register Write
VIH
VIL
0VIH
VIL
In1
1. If 8-bit data transfer mode is enabled.
In 8-bit data transfer mode, High Byte is undefined for Data Out. For Data In, X can be VIH or VIL, but no other value.
In
Data Register Read
VIH
VIL
0VIL
VIH
Out
Control Register Write
VIL
VIH
6H
VIH
VIL
X
Control In
Alt Status Read
VIL
VIH
6H
VIL
VIH
High Z
Status Out
T7.0 1382
1382 F01.0
VDD/POR#
TR
90%
10%
TF
90%
10%
相關(guān)PDF資料
PDF描述
SST85LD1001T-60-RI-LBTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
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