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參數(shù)資料
| 型號： | SST55VD020-60-I-TQWE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, ROHS COMPLIANT, MS-026, TQFP-100 |
| 文件頁數(shù)： | 17/45頁 |
| 文件大小： | 666K |
| 代理商： | SST55VD020-60-I-TQWE |
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24
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
Word 66: Device Recommended Multi-word DMA Cycle Time
This field defines the NAND Controller recommended Multi-word DMA transfer cycle time. This field defines, in
nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple
sector READ DMA or WRITE DMA command for any location on the media under nominal conditions. If a host
runs at a faster cycle rate by operating at a cycle time of less than this value, the NAND Controller may negate
DMARQ for flow control. The rate at which DMARQ is negated could result in reduced throughput despite the
faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher
performance may result. SST’s NAND Controller supports up to Multi-word DMA Mode-2, so this field is set to
120 ns.
Word 67: Minimum PIO Transfer Cycle Time Without Flow Control
This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guarantees data
integrity during the transfer without utilization of IORDY flow control. If this field is supported, Bit 1 of word 53
shall be set to one.The NAND Controller’s minimum cycle time is 120 ns. A value of 0078H is reported.
Word 68: Minimum PIO Transfer Cycle Time With IORDY
This field defines, in nanoseconds, the minimum cycle time that the device supports while performing data
transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. The
NAND Controller’s minimum cycle time is 120 ns, e.g., PIO Mode-4. A value of 0078H is reported.
Word 80: Major Version Number
If not 0000H or FFFFH, the device claims compliance with the major version(s) as indicated by bits (6:1) being
set to one. Since ATA standards maintain downward compatibility, a device may set more than one bit.
SST55VD020 supports ATA-1 to ATA-6.
Word 81: Minor Version Number
If an implementer claims that the revision of the standard they used to guide their implementation does not
need to be reported or if the implementation was based upon a standard prior to the ATA-3 standard, word 81
should be 0000H or FFFFH.
A value of 0019H reported in word 81 indicates ATA/ATAPI-6 T13 1410D revision 3a guided the
implementation.
Words 82-84: Features/command sets supported
Words 82, 83, and 84 indicate the features and command sets supported. A value of 706BH is reported.
Word 82
Bit
Function
15
0: Obsolete
14
1: NOP command is supported
13
1: Read Buffer command is supported
12
1: Write Buffer command is supported
11
0: Obsolete
10
0: Host Protected Area feature set is not supported
9
0: Device Reset command is not supported
8
0: Service interrupt is not supported
7
0: Release interrupt is not supported
6
1: Look-ahead is supported
5
1: Write cache is supported
4
0: Packet Command feature set is not supported
3
1: Power Management feature set is supported
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相關(guān)代理商/技術(shù)參數(shù) |
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| SST55VD020-60-I-TQWE-TM024 | 功能描述:閃存 ATA Media 60MHz 3.3V Industrial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST58LD008 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
| SST58LD008-70-C-P1H | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
| SST58LD016 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
| SST58LD016-70-C-P1H | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
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