- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365728 > SST49LF080A (Silicon Storage Technology, Inc.) 8 Mbit LPC Flash PDF資料下載
參數(shù)資料
| 型號： | SST49LF080A |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | 8 Mbit LPC Flash |
| 中文描述： | 8兆位LPC閃光 |
| 文件頁數(shù)： | 11/49頁 |
| 文件大?。?/td> | 579K |
| 代理商： | SST49LF080A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Data Sheet
8 Mbit LPC Flash
SST49LF080A
11
2003 Silicon Storage Technology, Inc.
S71235-00-000
4/03
CE#
The CE# pin, enables and disables the SST49LF080A,
controlling read and write access of the device. To enable
the SST49LF080A, the CE# pin must be driven low one
clock cycle prior to LFRAME# being driven low. The device
will enter standby mode when internal Write operations are
completed and CE# is high.
LFRAME#
The LFRAME# signifies the start of a (frame) bus cycle or
the termination of an undesired cycle. Asserting LFRAME#
for two or more clock cycle and driving a valid START value
on LAD[3:0] will initiate device operation. The device will
enter standby mode when internal operations are com-
pleted and LFRAME# is high.
TBL#, WP#
The Top Boot Lock (TBL#) and Write Protect (WP#) pins
are provided for hardware write protection of device mem-
ory. The TBL# pin is used to Write-Protect 16 boot sectors
(64 KByte) at the highest memory address range for the
SST49LF080A. The WP# pin write protects the remaining
sectors in the flash memory.
An active low signal at the TBL# pin prevents Program and
Erase operations of the top boot sectors. When TBL# pin is
held high, the write protection of the top boot sectors is dis-
abled. The WP# pin serves the same function for the
remaining sectors of the device memory. The TBL# and
WP# pins write protection functions operate independently
of one another.
Both TBL# and WP# pins must be set to their required pro-
tection states prior to starting a Program or Erase opera-
tion. A logic level change occurring at the TBL# or WP# pin
during a Program or Erase operation could cause unpre-
dictable results.
INIT#, RST#
A V
IL
on INIT# or RST# pin initiates a device reset. INIT#
and RST# pins have the same function internally. It is
required to drive INIT# or RST# pins low during a system
reset to ensure proper CPU initialization. During a Read
operation, driving INIT# or RST# pins low deselects the
device and places the output drivers, LAD[3:0], in a high-
impedance state. The reset signal must be held low for a
minimal duration of time T
RSTP
. A reset latency will occur if
a reset procedure is performed during a Program or Erase
operation. See Table 17, Reset Timing Parameters for
more information. A device reset during an active Program
or Erase will abort the operation and memory contents may
become invalid due to data being altered or corrupted from
an incomplete Erase or Program operation.
System Memory Mapping
The LPC interface protocol has address length of 32-bit or
4 GByte. The SST49LF080A will respond to addresses in
the range as specified in Table 4.
Refer to “Multiple Device Selection” section for more detail
on strapping multiple SST49LF080A devices to increase
memory densities in a system and “Registers” section on
valid register addresses.
TABLE
4: A
DDRESS
D
ECODING
R
ANGE
ID Strapping
Device #0 - 3
Device Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Address Range
FFFF FFFFH : FFC0 0000H
FFBF FFFFH : FF80 0000H
FF7F FFFFH : FF40 0000H
FF3F FFFFH : FF00 0000H
FEFF FFFFH : FEC0 0000H
FEBF FFFFH : FE80 0000H
FE7F FFFFH : FE40 0000H
FE3F FFFFH : FE00 0000H
000F FFFFH : 000E 0000H
Memory Size
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
128 KByte
Device #4 - 7
Device #8 - 11
Device #12 - 15
Device #0
1
1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
T4.0 1235
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST49LF080A-33-4C-NH | 8 Mbit LPC Flash |
| SST49LF080A-33-4C-WH | 8 Mbit LPC Flash |
| SST502 | Current Regulator Diode(穩(wěn)壓電流為0.43mA的電流穩(wěn)壓二極管) |
| SST505 | Current Regulator Diode(穩(wěn)壓電流為1.00mA的電流穩(wěn)壓二極管) |
| SST506 | Current Regulator Diode(穩(wěn)壓電流為1.40mA的電流穩(wěn)壓二極管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST49LF080A_06 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:8 Mbit LPC Flash |
| SST49LF080A-33-4C-NH | 功能描述:閃存 1M X 8 33MHz RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST49LF080A-33-4C-NHE | 功能描述:閃存 1M X 8 33MHz RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST49LF080A-33-4C-NHE-T | 功能描述:閃存 8M (1Mx8) 33MHz 3.0-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST49LF080A-33-4C-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:8 Mbit LPC Flash |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。