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參數(shù)資料
| 型號： | SST49LF020-33-4C-WH |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 2 Megabit LPC Flash |
| 中文描述： | 256K X 8 FLASH 3V PROM, 11 ns, PDSO32 |
| 封裝： | 8 X 14 MM, MO-142BA, TSOP1-32 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 724K |
| 代理商： | SST49LF020-33-4C-WH |
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22
Advance Information
4 Mbit LPC Flash
SST49LF040
2001 Silicon Storage Technology, Inc.
S71213-00-000
11/01 562
TABLE 17: I
NTERFACE
M
EASUREMENT
C
ONDITION
P
ARAMETERS
Symbol
V
TH1
V
TL1
V
TEST
V
MAX1
Input Signal Edge Rate
Value
0.6 V
DD
0.2 V
DD
0.4 V
DD
0.4 V
DD
1 V/ns
Units
V
V
V
V
T17.0 562
1. The input test environment is done with 0.1 V
DD
of overdrive over V
IH
and V
IL
. Timing parameters must be met with no more over-
drive than this. V
MAX
specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use
different voltage values, but must correlate results back to these parameters
TABLE 18: S
TANDARD
LPC M
EMORY
C
YCLE
D
EFINITION
(LPC M
ODE
)
Field
START
No. of Clocks
1
1
Description
“0000b” appears on LPC bus to indicate the start of cycle
Cycle Type: Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1
indicates the type of transfer “0” for Read, “1” for write. DIR: Indicates the direction of the
transfer. “0b” for Read, “1b” for Write. Bit 0 is reserved. “010Xb” indicates memory Read
cycle; while “011xb” indicates memory Write cycle.
The last component driving LAD[3:0] will drive it to “1111b” during the first clock, and tri-
state it during the second clock.
Address Phase for Memory Cycle. LPC supports the 32-bit address protocol. The
addresses transfer most significant nibble first and least significant nibble last. (i.e.,
Address[31:28] on LAD[3:0] first, and Address[3:0] on LAD[3:0] last.)
Synchronize to host or peripheral by adding wait states. “0000b” means Ready, “0101b”
means Short Wait, “0110b” means Long Wait, “1001b” for DMA only, “1010b” means
error, other values are reserved. The SST49LF040 only supports “Ready” sync.
Data Phase for Memory Cycle.
The data transfer least significant nibble first and most significant nibble last.
(i.e., DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.)
CYCTYPE + DIR
TAR
2
ADDR
8
Sync
N
Data
2
T18.1 562
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST49LF040-33-4C-NH | 4 Mbit LPC Flash |
| SST49LF040-33-4C-WH | 4 Mbit LPC Flash |
| SST49LF080A | 8 Mbit LPC Flash |
| SST49LF080A-33-4C-NH | 8 Mbit LPC Flash |
| SST49LF080A-33-4C-WH | 8 Mbit LPC Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST49LF020A | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit LPC Flash |
| SST49LF020A-33-4C-NHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit LPC Flash |
| SST49LF020A-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit LPC Flash |
| SST49LF030A | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:3 Mbit LPC Flash |
| SST49LF030A-33-4C-NH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:3 Mbit LPC Flash |
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