參數(shù)資料
型號： SST49LF008A-33-4C-NH
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： PROM
英文描述： 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
中文描述： 1M X 8 FLASH 3V PROM, 11 ns, PQCC32
封裝： PLASTIC, LCC-32
文件頁數(shù)： 3/36頁
文件大?。?/td> 412K
代理商： SST49LF008A-33-4C-NH
Advance Information
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
3
2001 Silicon Storage Technology, Inc.
S71161-06-000
9/01
504
FIGURE 1: S
INGLE
-B
YTE
R
EAD
W
AVEFORMS
TABLE
1: FWH R
EAD
C
YCLE
Clock
Cycle
1
Field
Name
START
Field Contents
FWH[3:0]
1
1101
FWH[3:0]
Direction
IN
Comments
FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transitioning high) should be
recognized. The START field contents indicate a FWH
memory read cycle.
Indicates which FWH device should respond. If the to IDSEL (ID
select) field matches the value ID[3:0], then that particular device
will respond to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
A field of this size indicates how many bytes will be or trans-
ferred during multi-byte operations. The SST49LF00xA will
only support single-byte operation. IMSIZE=0000b
In this clock cycle, the master (Intel ICH) has driven the bus
then float to all ‘1’s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
The SST49LF00xA takes control of the bus during this
cycle. During the next clock cycle, it will be driving “sync
data.”
During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant nibble of
the least-significant byte will be available during the next
clock cycle.
YYYY is the least-significant nibble of the least-significant
data byte.
YYYY is the most-significant nibble of the least-significant
data byte.
In this clock cycle, the SST49LF00xA has driven the bus to
all ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
The master (Intel ICH) resumes control of the bus during
this cycle.
2
IDSEL
0000 to 1111
IN
3-9
IMADDR
YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11
TAR0
1111
IN
then Float
12
TAR1
1111 (float)
Float
then OUT
13
RSYNC
0000 (READY)
OUT
14
DATA
YYYY
OUT
15
DATA
YYYY
OUT
16
TAR0
1111
OUT
then Float
17
TAR1
1111 (float)
Float then
IN
T1.3 504
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
FWH4
FWH[3:0]
504 ILL F59.1
STR
TAR
RSYNC
IMS
IMADDR
IDS
DATA
TAR
相關(guān)PDF資料
PDF描述
SST49LF008A-33-4C-WH 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF004B 4 Mbit LPC Firmware Flash
SST49LF004B-33-4C-EI 4 Mbit LPC Firmware Flash
SST49LF004B-33-4C-EIE 4 Mbit LPC Firmware Flash
SST49LF004B-33-4C-NH 4 Mbit LPC Firmware Flash
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SST49LF008A-33-4C-NHE 功能描述:閃存 8M (1Mx8) 33MHz Commercial Temp RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
SST49LF008A-33-4C-NHE_ 制造商:Microchip Technology Inc 功能描述:
SST49LF008A-33-4C-NHE-T 功能描述:閃存 8M (1Mx8) 33MHz 3.0-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
SST49LF008A-33-4C-NHE-T-CUT TAPE 制造商:Microchip 功能描述:SST49LF Series 8 Mbit 1024 K x 8 3.3 V Firmware Hub - PLCC-32
SST49LF008A-33-4C-WH 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
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