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參數(shù)資料
| 型號(hào)： | SST45VF512-10-4C-SA |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 512K X 1 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 4.90 X 6 MM, SOIC-8 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SST45VF512-10-4C-SA |
2
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
F
UNCTIONAL
B
LOCK
D
IAGRAM
Reset
Reset will terminate any operation, e.g., Read, Erase
and Program, in progress. It is activated by a high to low
transition on the RESET# pin. The device will remain in
reset condition as long as RESET# is low. Minimum reset
time is 10μs. See Figure 14 for reset timing diagram.
RESET# is internally pulled-up and could remain uncon-
nected during normal operation. After reset, the device is
in standby mode, a high to low transition on CE# is
required to start the next operation.
An internal power-on reset circuit protects against acci-
dental data writes. Applying a logic level low to RESET#
during the power-on process then changing to a logic
level high when V
DD
has reached the correct voltage
level will provide additional protection against accidental
writes during power on.
Read SST ID/Read Device ID
The Read SST ID and Read Device ID operations read
the JEDEC assigned manufacturer identification and the
manufacturer assigned device identification codes.
These codes may be used to determine the actual device
resident in the system.
Write Protect
The WP# pin provides inadvertent write protection. The
WP# pin must be held high for any Erase or Program
operation. The WP# pin is “don’t care” for all other
operations. In typical use, the WP# pin is connected to
V
SS
with a standard pull-down resistor. WP# is then
driven high whenever an Erase or Program operation is
required. If the WP# pin is tied to V
DD
with a pull-up
resistor, then all operations may occur and the write
protection feature is disabled. The WP# pin has an
internal pull-up and could remain unconnected when not
used.
514ILL B1.0
I/O Buffers
and
Data Latches
SuperFlash
Cell Array
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK
SI
SO
WP# RESET#
Serial Interface
T
ABLE
1: P
RODUCT
I
DENTIFICATION
Byte
0000 H
Data
BF H
Manufacturer
’
s ID
Device ID
SST45VF512
SST45VF010
SST45VF020
0001 H
0001 H
0001 H
41 H
45 H
43 H
514 PGM T1.4
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參數(shù)描述 |
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| SST-48-03/FR/97 | 功能描述:熱收縮管和套管 HS-TUBING .3" FR BK PRICE PER PC RoHS:否 制造商:3M Electronic Specialty 類型:Tubing 材料:Polyolefin, Flexible 顏色:Clear 最低收縮溫度:+ 100 C 恢復(fù)直徑: 長(zhǎng)度:100 ft 內(nèi)徑:1.5 in 收縮率:2:1 |
| SST-48-04/97 | 功能描述:熱收縮管和套管 RoHS:否 制造商:3M Electronic Specialty 類型:Tubing 材料:Polyolefin, Flexible 顏色:Clear 最低收縮溫度:+ 100 C 恢復(fù)直徑: 長(zhǎng)度:100 ft 內(nèi)徑:1.5 in 收縮率:2:1 |
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| SST-48-04/FR/97/NM | 制造商:TE Connectivity 功能描述:CS9367-000 |
| SST-48-04/FR/97-CS8407 | 制造商:TE Connectivity 功能描述:SST-48-04/FR/97-CS8407 |
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