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參數(shù)資料
| 型號： | SST39W800A-90-4C-C2KE |
| 廠商： | Silicon Storage Technology, Inc. |
| 元件分類： | FLASH |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 64兆位（x16）的多功能閃存加 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 357K |
| 代理商： | SST39W800A-90-4C-C2KE |
Data Sheet
8 Mbit Multi-Purpose Flash
SST39WF800A
3
2006 Silicon Storage Technology, Inc.
S71258-05-000
7/06
Write Operation Status Detection
The SST39WF800A provides two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile Write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both Reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
7
)
When the SST39WF800A is in the internal Program oper-
ation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 μs
.
During internal Erase oper-
ation, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is completed, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 0-1 for Tog-
gle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39WF800A provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39WF800A provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within T
. The contents of DQ
15
-
DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39WF800A also contains the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. See Figure 11 for the timing diagram. Once the
device enters the CFI Query mode, the system can read
CFI data at the addresses given in Tables 5 through 7. The
system must write the CFI Exit command to return to Read
mode from the CFI Query mode.
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| SST39WF1601-70-4C-B3KE | 功能描述:閃存 16M (1Mx16) 70ns 1.65-1.95V Comm RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF1601-70-4C-B3KE_ | 制造商:Microchip Technology Inc 功能描述: |
| SST39WF1601-70-4C-B3KE-T | 功能描述:閃存 1.65V to 1.95V 16mb Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF1601-70-4C-MAQE | 功能描述:閃存 1.65V to 1.95V 16mb Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39WF1601-70-4C-MAQE-T | 功能描述:閃存 1.65V to 1.95V 16Mbit Multi-Prps Fl RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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