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參數(shù)資料
| 型號： | SST39SF512-70-4I-WHE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 64K X 8 FLASH 5V PROM, 70 ns, PDSO32 |
| 封裝： | 8 X 14 MM, LEAD FREE, MO-142BA, TSOP1-32 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 275K |
| 代理商： | SST39SF512-70-4I-WHE |
Data Sheet
512 Kbit Multi-Purpose Flash
SST39SF512
3
2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
Data# Polling (DQ
7
)
When the SST39SF512 are in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. Note that even thought DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 μs. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program Operation. For sector or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with “1”. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39SF512 provide both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39SF512 provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three byte sequence. The three-
byte load sequence is used to initiate the Program opera-
tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-
byte load sequence. The SST39SF512 device is shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode, within T
RC.
Product Identification
The Product Identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details,
Table 4 for software operation, Figure 11 for the software ID
entry and read timing diagram and Figure 17 for the ID
entry command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
BFH
Manufacturer’s ID
Device ID
SST39SF512
0001H
B4H
T1.3 1149
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SST39SF512-90-4C-NH | 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39SF512-90-4C-PH | 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39SF512-90-4C-U3 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit (x8) Multi-Purpose Flash |
| SST39SF512-90-4C-WH | 功能描述:閃存 U 804-39SF5127CWH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39SF512-90-4I-NH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit (x8) Multi-Purpose Flash |
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