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參數(shù)資料
| 型號： | SST37VF512-90-3C-WH |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 64K X 8 FLASH 2.7V PROM, 90 ns, PDSO32 |
| 封裝： | 8 X 14 MM, MO-142BA, TSOP1-32 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 165K |
| 代理商： | SST37VF512-90-3C-WH |
6
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
2001 Silicon Storage Technology, Inc.
S71151-02-000
5/01
397
TABLE
4: R
EAD
M
ODE
DC O
PERATING
C
HARACTERISTICS
V
DD
=2.7-3.6V
(Ta = 0
°
C to +70
°
C (Commercial))
Symbol
I
DD
Parameter
V
DD
Read Current
Limits
Max
Test Conditions
Address input=V
IL
/V
IH
, at f=1/T
RC
Min
V
DD
=V
DD
Max
CE#=OE#=V
IL
, all I/Os open
CE#=V
IHC
, V
DD
=V
DD
Max
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
V
DD
=V
DD
Max
I
OL
=100 μA, V
DD
=V
DD
Min
I
OH
=-100 μA, V
DD
=V
DD
Min
CE#=OE#=V
IL
, A
9
=V
H
Max
Min
Units
12
15
1
10
0.8
mA
μA
μA
μA
V
V
V
V
V
μA
I
SB
I
LI
I
LO
V
IL
V
IH
V
IHC
V
OL
V
OH
I
H
Standby V
DD
Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
Supervoltage Current for A
9
for Read-ID
0.7 V
DD
V
DD
-0.3
0.2
V
DD
-0.3
200
T4.3 397
TABLE
5: P
ROGRAM
/E
RASE
DC O
PERATING
C
HARACTERISTICS
V
DD
=2.7-3.6V
(Ta = 25
°
C±5
°
C)
Symbol Parameter
I
DD
V
DD
Erase or Program Current
I
LI
Input Leakage Current
I
LO
Output Leakage Current
V
H
Supervoltage for A
9
and OE#
I
H
Supervoltage Current for A
9
and OE#
Limits
Max
20
1
10
12.6
200
Test Conditions
CE#=V
IL,
OE#=V
H
, V
DD
=V
DD
Max, WE#=V
IL
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
Min
Units
mA
μA
μA
V
μA
11.4
OE#=V
H
Max, A
9
=V
H
Max, V
DD
=V
DD
Max, CE# = V
IL
T5.1 397
TABLE
6: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
T
PU-READ1
T
PU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Write Operation
Minimum
100
100
Units
μs
μs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T6.1 397
TABLE
7: C
APACITANCE
(Ta = 25
°
C, f=1 Mhz, other pins open)
Parameter
C
I/O1
C
IN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
12 pF
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T7.0 397
TABLE
8: R
ELIABILITY
C
HARACTERISTICS
Symbol
N
END1
T
DR1
I
LTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
100
100 + I
DD
T8.3 397
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