參數(shù)資料
型號： SST34HF3223B-90-4C-LP
英文描述： MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
中文描述： 混合存儲器|靜態(tài)存儲器EEPROM中|的CMOS | BGA封裝| 56PIN |塑料
文件頁數(shù)： 7/32頁
文件大?。?/td> 486K
代理商： SST34HF3223B-90-4C-LP
Data Sheet
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
7
2001 Silicon Storage Technology, Inc.
S71172-05-000
10/01 523
FIGURE 2: P
IN
A
SSIGNMENTS
FOR
56-
BALL
LFBGA (8
MM
X
10
MM
) C
OMBO
M
EMORY
P
INOUT
TABLE
2: P
IN
D
ESCRIPTION
Symbol
A
MS1
to A
0
Pin Name
Address Inputs
Functions
To provide flash address, A
19
-A
0
.
To provide SRAM address, A
16
-A
0
for 2M and A
17
-A
0
for 4M
To provide SRAM address input in byte mode (x8). When CIOs is V
IL
, the SRAM is in
Byte mode and SA provides the most significant address input. When CIOs is V
IH
, the
SRAM is in Word mode and SA becomes a Don’t Care pin.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
To activate the Flash memory bank when BEF# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high
Output Enable
To gate the data output buffers
Write Enable
To control the Write operations
Upper Byte Control (SRAM)
To enable DQ
15
-DQ
8
Lower Byte Control (SRAM)
To enable DQ
7
-DQ
0
I/O Configuration (SRAM)
CIOs = V
IH
is Word mode (x16), CIOs = V
IL
is Byte mode (x8)
Write Protect
To protect and unprotect sectors from Erase or Program operation
Reset
To Reset and return the device to Read mode
Ready/Busy#
To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10K
- 100K
pull-up resistor is required to
allow RY/BY# to transition high indicating the device is ready to read.
Ground
Power Supply (Flash)
2.7-3.3V Power Supply to Flash only
Power Supply (SRAM)
2.7-3.3V Power Supply to SRAM only
No Connection
Unconnected pins
1. A
MS
= Most Significant Address
SA
Address Input (SRAM)
DQ
15
-DQ
0
Data Inputs/Outputs
BEF#
BES1#
BES2
OE#
WE#
UBS#
LBS#
CIOs
WP#
RST#
RY/BY#
Flash Memory Bank Enable
V
SS
V
DD
F
V
DD
S
NC
T2.5 523
523 56-lfbga ILL P01.2
A11
A8
WE#
WP#
LBS#
A7
A15
A12
A19
BES2
RST#
UBS#
A6
A3
NC
A13
A9
NC
RY/BY#
A18
A5
A2
NC
A14
A10
A17
A4
A1
A16
SA
DQ6
DQ1
VSS
A0
NC
DQ15
DQ13
DQ4
DQ3
DQ9
OE#
BEF#
VSS
DQ7
DQ12
VDDS
VDDF
DQ10
DQ0
BES1#
DQ14
DQ5
CIOs
DQ11
DQ2
DQ8
A B C D E F G H
SST34HF1621/1641
8
7
6
5
4
3
2
1
TOP VIEW (balls facing down)
相關(guān)PDF資料
PDF描述
SST34HF3223B-90-4E-LP CY8C21634 PSoC Mixed Signal Arrays; Analog PSoC Blocks: 4 Type "E"; Digital PSoC Blocks: 2-Basic 2-Comms; Memory Size: 8KB Flash; Temperature Range: -40C to +85C; # of I/O Pins: 26; # of Pins/Ball: 32; RAM: 512bytes; Vcc (V): 2.4V to 5.25V; Package: MLF
SST34HF3243B-70-4C-LP One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
SST34HF3243B-70-4E-LP KIT ISR PROGRAMMING NO WARP
SST34HF1621-70-4C-LFP 16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621-70-4E-L1P 16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SST34HF3223B-90-4E-LP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-70-4C-LP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-70-4E-LP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-90-4C-LP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-90-4E-LP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
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