參數(shù)資料
型號： SST32HF1641
廠商： Silicon Storage Technology, Inc.
元件分類： 組合存儲器
英文描述： Multi-Purpose Flash Plus + SRAM ComboMemory
中文描述： 多功能閃存容量的SRAM ComboMemory
文件頁數(shù)： 12/36頁
文件大小： 413K
代理商： SST32HF1641
12
Preliminary Specifications
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281
SST32HF1621C / SST32HF1641C / SST32HF3241C
2005 Silicon Storage Technology, Inc.
S71236-04-000
5/05
TABLE
6: DC O
PERATING
C
HARACTERISTICS
(V
DD
= V
DDF
AND
V
DDS
= 2.7-3.3V)
Symbol
I
DD
Parameter
Active V
DD
Current
Limits
Max
Test Conditions
Address input = V
ILT
/V
IHT,
at f=5 MHz,
V
DD
=V
DD
Max, all DQs open
OE#=V
IL
, WE#=V
IH
BEF#=V
IL
, BES1#=V
IH
,
or BES2=V
IL
BEF#=V
IH
, BES1#=V
IL ,
BES2=V
IH
BEF#=V
IH
, BES1#=V
IL ,
BES2=V
IH
WE#=V
IL
BEF#=V
IL
, BES1#=V
IH
,
or BES2=V
IL
, OE#=V
IH
BEF#=V
IH
, BES1#=V
IL ,
BES2=V
IH
V
DD
= V
DD
Max, BEF#=BES1#=V
IHC
,
BES2=V
ILC
Min
Units
Read
Flash
SRAM
18
30
40
mA
mA
mA
Concurrent Operation
Write
1
Flash
SRAM
Standby V
DD
Current SST32HFx1
35
30
110
30
30
1
10
0.8
0.3
mA
mA
μA
μA
μA
μA
μA
V
V
V
V
V
V
V
V
I
SB
SST32HFx1C
I
RT
I
LI
I
LO
V
IL
V
ILC
V
IH
V
IHC
V
OLF
V
OHF
V
OLS
V
OHS
Reset
V
DD
Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
Reset=V
SS
±0.3V
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
V
DD
=V
DD
Max
V
DD
=V
DD
Max
I
OL
=100 μA, V
DD
=V
DD
Min
I
OH
=-100 μA, V
DD
=V
DD
Min
IOL =1 mA, V
DD
=V
DD
Min
IOH =-500 μA, V
DD
=V
DD
Min
0.7
V
DD
V
DD
-0.3
0.2
V
DD
-0.2
0.4
2.2
T6.1 1236
1. I
DD
active while Erase or Program is in progress.
TABLE
7: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
T
PU-READ1
T
PU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Program/Erase Operation
Minimum
100
100
Units
μs
μs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T7.0 1236
TABLE
8: C
APACITANCE
(T
A
= 25°C, f=1 Mhz, other pins open)
Parameter
C
I/O1
C
IN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
12 pF
12 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T8.0 1236
TABLE
9: F
LASH
R
ELIABILITY
C
HARACTERISTICS
Symbol
N
END1
T
DR1
I
LTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
100
100 + I
DD
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T9.0 1236
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