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參數(shù)資料
| 型號(hào)： | SST32HF162-70-4C-TBK |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA48 |
| 封裝： | 10 X 12 MM, 1.20 MM HEIGHT, TBGA-48 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 342K |
| 代理商： | SST32HF162-70-4C-TBK |
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Data Sheet
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
3
2001 Silicon Storage Technology, Inc.
S71171-05-000
8/01
520
are latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the rising
edge of either BEF# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once initi-
ated, will be completed, within 20 μs. See Figures 7 and 8
for WE# and BEF# controlled Program operation timing
diagrams and Figure 18 for flowcharts. During the Program
operation, the only valid flash Read operations are Data#
Polling and Toggle Bit. During the internal Program opera-
tion, the host is free to perform additional tasks. Any SDP
commands loaded during the internal Program operation
will be ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF802/162/164 offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A
19
-A
11
, for SST32HF162/164, and A
18
-A
11
, for
SST32HF802, are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A
19
-A
15
, for SST32HF162/164, and A
18
-A
15
,
for SST32HF802, are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 12
and 13 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Flash Chip-Erase Operation
The SST32HF802/162/164 provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 10 for timing diagram,
and Figure 21 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF802/162/164 provide two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6.
In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Flash Data# Polling (DQ
7
)
When the SST32HF802/162/164 flash memory banks are
in the internal Program operation, any attempt to read DQ
7
will produce the complement of the true data. Once the
Program operation is completed, DQ
7
will produce true
data. Note that even though DQ
7
may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles. During internal Erase operation,
any attempt to read DQ
7
will produce a ‘0’. Once the inter-
nal Erase operation is completed, DQ
7
will produce a ‘1’.
The Data# Polling is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operation. For Sector- or
Block-Erase, the Data# Polling is valid after the rising edge
of the sixth WE# (or BEF#) pulse. See Figure 9 for Data#
Polling timing diagram and Figure 19 for a flowchart.
Flash Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
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| SST32HF162-70-4E-EK | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| SST32HF162-70-4E-L3K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|48PIN|PLASTIC |
| SST32HF162-70-4E-LBK | 功能描述:組合存儲(chǔ)器 16M FLASH 2M SRAM RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| SST32HF162-70-4E-LBKE | 功能描述:組合存儲(chǔ)器 16M FLASH 2M SRAM RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| SST32HF162-70-4E-TBK | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
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