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參數(shù)資料
| 型號： | SSP-21110-015-883B |
| 英文描述： | Power Control/Management |
| 中文描述： | 電源控制/管理 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 80K |
| 代理商： | SSP-21110-015-883B |
FUNCTIONAL DESCRIPTION
The SSP-21120 Series of Solid-State Power Controller Modules
incorporate the wire protection feature of electromechanical cir-
cuit breakers and the reliability of solid-state relays. In addition
to the solid-state relay's input logic compatibility, the SSP-21120
series provide logic compatible status outputs.
A TTL/CMOS compatible input provides external control of the
power switch's "ON/OFF" state. A logic high on this control input
turns the power to the load "on." A logic low will turn the power
switch off, which removes power from the load.
In the event of an overload, the SSP-21120 series will trip, just
like a circuit breaker, and automatically remove power from the
load. In order to turn back on, the control input must be brought
to a logic low, and then returned to a logic high state.
As in a circuit breaker, the SSPC's time to trip depends on the
current level.
Slight overloads will cause longer trip times.
Heavy overloads will cause shorter trip times. The fault ("Instant
Trip") and I
2
T trip curve, FIGURE 2, shows the trip time as a
function of current for a single trip or repetitive trips with at least
10 milli-seconds between trip and turn on. Attempts to repeat-
edly turn on into an overload will result in the thermal memory
shortening each trip time. This "memory" protects the wire, load,
and the Solid-State Power Controller module.
The status lines are TTL/CMOS compatible outputs which reflect
the state of the SSPC, the load and the Built-In-Test (BIT) cir-
cuits. The status permits an external subsystem to monitor and
ultimately control the SSPC. TABLE 5 defines the status lines
states which indicate the various states of the SSPC. Further
explanation of the status lines appears in the applications infor-
mation section.
The SSP-21120 series are characterized by their curent rating
and maximum "on" resistance listed in TABLE 4. These para-
meters are established by the number of Power FETs placed in
parallel within the FET Hybrid.
The trip function is implemented by two separate circuits, a true
I
2
T trip comparator and a short-circuit fault comparator. They are
independent of each other but work together to protect the sys-
tem.
If the load current is less than 110% of rated current, the SSPC
will never trip. If the load current is greater than 145%, the SSPC
will always trip.
For load currents less than 600%, the trip time can be found from
FIGURE 2 by drawing a horizontal line on FIGURE 2 at the cur-
rent level of interest.
The SSPC will always trip at a time
between the two curves. This is true I
2
T tripping.
When the SSPC trips in accordance with the I
2
T characteristics,
the fall time is 200 μs, maximum.
For load currents greater than 1500%, the SSPC will turn off in
less than 25 μs. Between 1000% and 1500%, the SSPC will turn
off in a time less than the"max.trip limit" shown in FIGURE 2 and
may turn off in less than 25 μs.
3
10,000
1,000
800
600
400
200
0
10
1.0
0.001
0.1
0.01
25
μ
s
145%
110%
L
TIME - SECONDS
NEVER TRIP
MAX. TRIP LIMIT
MIN. TRIP LIMIT
ALWAYS TRIP
INSTANT
TRIP
1,500
FIGURE 2.TRIP CHARACTERISTICS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSP-21110-015-B | Power Control/Management |
| SSP-21110-020 | Power Control/Management |
| SSP-21110-020-883B | Power Control/Management |
| SSP-21110-020-B | Power Control/Management |
| SSP-21110-025 | Power Control/Management |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSP-21110-015-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Control/Management |
| SSP-21110-020 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Control/Management |
| SSP-21110-020-883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Control/Management |
| SSP-21110-020-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Control/Management |
| SSP-21110-025 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Control/Management |
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