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| 型號： | SSM2518CPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUD PWR 2C STER D 20LFCSP |
| 標準包裝： | 1,500 |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 2.5W x 2 @ 4 歐姆 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 特點： | 消除爆音，數(shù)字輸入，I²C，I²S，靜音，短路和熱保護，關機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 20-LFCSP-WQ（4x4） |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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SSM2518
Data Sheet
Rev. A | Page 14 of 48
THEORY OF OPERATION
The SSM2518 is fully integrated 2-channel digital input, Class-D
output audio amplifier. The SSM2518 receives digital audio input
and produces the PDM differential switching outputs using the
internal power stage. The part has built in protection for over-
temperature as well as overcurrent conditions. The SSM2518
also has built in soft turn on and soft turn off for pop-and-click
suppression. The part has programmable register control via the
I2C port.
POWER SUPPLIES
The SSM2518 requires two power supplies: PVDD and DVDD.
Descriptions of each of these supplies follow.
PVDD
The PVDD pin supplies power to the full bridge power stage
of a MOSFET and its associated drive, control, and protection
circuitry. PVDD can operate from 2.5 V to 5.5 V and must be
present to obtain audio output. Lowering the supply PVDD
results in lower output power and, correspondingly, lower
power consumption but does not degrade audio performance.
DVDD
The DVDD pin provides power to the digital logic circuitry and
determines the input trip points. DVDD can operate from 1.62 V
to 3.6 V and must be present to obtain audio output. Lowering
the supply voltage of DVDD results in lower power consump-
tion but does not affect audio performance.
POWER-DOWN MODES
The SSM2518 offers a hardware shutdown pin, SD, which can
be used to set the IC to its lowest power state, with all blocks
disabled. This hardware shutdown mode is enabled when the
SD pin is pulled low.
When the hardware shutdown is removed, the IC begins in
software power-down mode, where all blocks except for the
I2C interface are disabled. To fully power up the amplifier, clear
S_RST (Bit 7 of Register 0x00). In addition to the software
power-down, the software master mute is enabled at the initial
state of the amplifier; therefore, no audio is output until Bit 0 of
Register 0x07 is cleared.
The left and right channels can be independently shut down
by setting setting L_PWDN and R_PWDN (Bit 1 and Bit 2,
respectively, in Register 0x09). Disabling a channel shuts down
the channel specific digital processing, DAC, Class-D modulator,
and power stage.
The SSM2518 also contains a smart power-down feature, which
is enabled by default. This feature can be disabled by clearing
APWDN_EN (Bit 0 in Register 0x09). When active, this feature
monitors the incoming digital audio signal. If this is zero for
1024 consecutive samples, regardless of sample rate, it puts the
IC in the smart power-down state wherein all blocks, except the
I2S and I2C ports, are placed in a low power state. Once a single
this state and resumes normal operation.
POWER-ON RESET/VOLTAGE SUPERVISOR
The SSM2518 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to all
circuitry whenever PVDD or DVDD is substantially below the
nominal operating threshold. This circuit simplifies supply
sequencing during initial power-on.
The circuit also monitors the power supplies to the SSM2518. If
the supply voltages fall below the nominal operating threshold,
this circuit stops the output and issues a reset. This ensures that
no damage occurs due to low voltage operation and that no pops
can occur under nearly any power removal condition.
MASTER AND BIT CLOCK
The SSM2518 requires an internal master clock to operate. This
clock must run at a frequency between 2.048 MHz and 6.144 MHz,
depending on the input sample rate, and it must be fully synchro-
nous with the incoming audio data. This clock signal can be
derived from either the MCLK or BCLK pin, depending on the
configuration used.
If the MCLK pin is used, the internal clock is derived by either
dividing, passing through, or doubling the external clock signal
as required. The clock supplied to the MCLK pin can range from
2.048 MHz to 38.864 MHz. In this case, the external MCLK pin
signal can run at various multiples of the audio sample rate (fS).
The relationship between the MCLK rate and the audio sample
rate is determined by the master clock select (MCS) register setting,
Bits[4:1] in Register 0x00. Table 11 provides a summary of the
available options.
In addition, a bit clock must run at the same rate as the incoming
audio data on the SDATA pin. This clock can be supplied to the
BCLK pin, or it can be generated internally by dividing MCLK.
In this case, when BCLK_GEN (Bit 7 of Register 0x03) is set, the
logic level of the BCLK pin is used to select the audio interface
BCLK rate. Tie the BCLK pin to DVDD for 16 clock cycles per
channel; tie it to ground for 32 cycles per channel.
If the system bit clock is in the range of acceptable internal
master clock frequencies (between 2.048 MHz and 6.144 MHz),
then it can serve as both master clock and bit clock. Setting
NO_BCLK (Bit 5 of Register 0x00) routes the signal on the
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| SSM2518CPZ-RL | 功能描述:IC AMP AUD PWR 2C STER D 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:DirectDrive® 類型:D 類 輸出類型:1-通道（單聲道），帶立體聲耳機 在某負載時最大輸出功率 x 通道數(shù)量:930mW x 1 @ 8 歐姆; 40mW x 2 @ 16 歐姆 電源電壓:2.7 V ~ 5.5 V 特點:消除爆音，差分輸入，I²C，靜音，關閉，音量控制 安裝類型:表面貼裝 供應商設備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) 其它名稱:MAX97000EWA+T-ND |
| SSM2519ACBZ-R7 | 功能描述:音頻放大器 Digital PDM Filterless Class D Mono Amp RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| SSM2519ACBZ-RL | 功能描述:音頻放大器 Digital PDM Filterless Class D Mono Amp RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| SSM2529ACBZ-R7 | 功能描述:音頻放大器 Digital Input Mono ClassD Audio Amp RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| SSM2529ACBZ-RL | 功能描述:音頻放大器 Digital Input Mono ClassD Audio Amp RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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