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參數(shù)資料
| 型號： | SSM2518CBZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/48頁 |
| 文件大小： | 0K |
| 描述： | IC AMP AUD PWR 2C STER D 16WLCSP |
| 產(chǎn)品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 10,000 |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 2.5W x 2 @ 4 歐姆 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 特點： | 消除爆音，數(shù)字輸入，I²C，I²S，靜音，短路和熱保護，關(guān)機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 16-WLCSP（2.21x2.21） |
| 封裝/外殼： | 16-WFBGA，WLCSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
SSM2518
Rev. A | Page 17 of 48
DIGITAL AUDIO INTERFACE
The SSM2518 operates as a slave on the serial audio interface.
It is capable of receiving stereo I2S-style, left justified, or right
justified data. Mono, stereo, and multichannel PCM/TDM
interface formats are available. The data format and interface
style are selected by adjusting the SDATA_FMT and SAI fields
in Register 0x02. Note that, when operating in right justified
mode, the proper data width must be chosen. The function of the
LRCLK pin varies depending on the data format. See Figure 26
through Figure 30 for the expected audio formats for various
configurations.
CHANNEL MAPPING
Stereo audio formats and TDM formats with 2, 4, 8, or 16
channels are available. In these modes, the amplifier left and
right audio can be independently chosen from any of the
available channels using the two fields in Register 0x04. For
most digital interface formats, many of these options are not
present. For example, in stereo modes, only Channel 0 and
Channel 1 are valid, and in four-slot TDM mode, only
Channel 0, Channel 1, Channel 2, and Channel 3 are valid.
SAMPLE RATE DETECTION
The SSM2518 can be configured to automatically detect the
sample rate, or the sample rate can be entered manually into the
FS field (Bit 1 and Bit 0 of Register 0x02). The choice of
automatic or manual sample rate detection is made by setting
the ASR bit (Bit 0 of Register 0x01). Sample rate detection
functions properly only when MCS (Bits[4:1] of Register 0x00)
is set correctly.
STANDALONE MODE
When the SAMOD pin is pulled high, the SSM2518 can operate
in several common stereo formats without any I2C control. Some
details of the serial audio interface can be configured by tying
In addition, the amplifier gain can be controlled via the ADDR pin.
Table 10. Standalone Mode Pin Functions
Pin
Standalone Function
Pin Options
SCL
FORMAT
Low: I2S
High: left justified
SDA
MCLK_SEL
Low: MCLK = 256 × fS
High: MCLK = 384 × fS
SD
Low: shutdown/mute
High: normal operation
ADDR
GAIN
Low: +12 dB digital gain
High: 0 dB digital gain
In standalone mode, the volume control, dynamic range control,
and EMI control features are disabled. Automatic sample rate
detection and smart power-down are enabled. All other settings
are set to their default values.
LOW POWER MODES
Two low power modes are available. If DAC_LPM (Bit 3 of
Register 0x09) is set, the digital-to-analog converter (DAC)
runs at half speed, reducing the quiescent current. This half
speed mode is also active when the MCS setting (Bits[4:1] of
Register 0x00) is set to its lowest value (MCS = 0000) because
the slowest acceptable MCLK rates can only support half speed
DAC operation.
If AMP_LPM (Bit 4 of Register 0x09) is set, the Σ-Δ modulator
runs in a special mode that offers lower quiescent current when
the output power is small, at the expense of slightly degraded
audio performance.
DYNAMIC RANGE CONTROL
The dynamic range control, or DRC, can be used to reduce the
dynamic range of the audio signal. A common DRC scheme
involves applying a gain reduction to large output signals, along
with a net increase in gain for moderate to small signals. The
qualitative result is a louder speaker output for moderate output
levels without the undesired effects of amplifier clipping or
speaker overdrive at high levels.
To calculate the gain adjustment, an rms detector gives the
average level of the input signal, based on the averaging time set
by RMS_TAV (Bits[3:0] in Register 0x12). Based on this time
averaged level, the overall gain is adjusted so that the input/
output characteristic matches the specified compression curve.
This curve can be represented by a log-to-log graph with five
distinct regions, as shown in Figure 25.
OU
T
P
U
T
INPUT
WITHOUT DRC
WITH DRC
NT
ET
CT
LT
SMAX
CT
ET
SMIN
WITHOUT DRC
WITH DRC
10
242
-032
Figure 25. DRC Compression Curve: Log-to-Log Representation of the DRC
Output Level vs. Input Level
From bottom left to top right, these regions (shown in red) are
the noise gate, expander, linear region, compressor, and limiter.
The control points between these regions can be set using the
DRC control registers (Register 0x0A through Register 0x12)
using the variable names (CT, ET, and so forth) as shown on the
plot axes in Figure 25. Each element can be individually enabled
using the LIM_EN, COMP_EN, EXP_EN, and NG_EN bits in
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