SSM2166
Data Sheet
Rev. E | Page 12 of 20
POWER-DOWN FEATURE
The supply current of the
SSM2166 can be reduced to less than
100 A by applying an active high, 5 V CMOS-compatible input
to the POWER DOWN pin (Pin 12). In this state, the input and
output circuitry of the
SSM2166 assumes a high impedance
state; as such, the potentials at the input pin and the output pin are
determined by the external circuitry connected to th
e SSM2166.T
he SSM2166 takes approximately 200 ms to settle from a power-
down to power-on command. For power-on to power-down,
the
SSM2166 requires more time, typically less than 1 second.
Cycling the power supply to th
e SSM2166 can result in quicker
settling times: the off-to-on settling time of the
SSM2166 is less
than 200 ms, while the on-to-off settling time is less than 1 ms.
In either implementation, transients may appear at the output of
the device. To avoid these output transients, use mute control of
the VCA gain as previously mentioned.
PCB LAYOUT CONSIDERATIONS
Because the
SSM2166 is capable of wide bandwidth operation
and can be configured for as much as 80 dB of gain, special care
must be exercised in the layout of the PCB that contains the IC
and its associated components. The following recommendations
should be considered and/or followed:
In some high system gain applications, the shielding of input
wires to minimize possible feedback from the output of the
SSM2166 back to the input circuit may be necessary.
A single-point (star) ground implementation is recom-
mended in addition to maintaining short lead lengths and
PCB runs. The evaluation board layout shown in
Figure 27,grounding scheme. In applications where an analog ground
surrounding circuitry should be connected to the analog
ground of the system. Because of these recommendations,
wire-wrap board connections and grounding
implementations should be avoided.
The internal buffer of th
e SSM2166 was designed to drive only
the input of the internal VCA and its own feedback network.
Stray capacitive loading to ground from the BUF OUT pin in
excess of 5 pF to 10 pF can cause excessive phase shift and
can lead to circuit instability.
When using high impedance sources (≥5 k), system gains
in excess of 60 dB are not recommended. This configuration
is rarely appropriate because virtually all high impedance
inputs provide larger amplitude signals that do not require
as much amplification. When using high impedance sources,
however, it can be advantageous to shunt the source with a
capacitor to ground at the input pin of the IC (Pin 7) to
lower the source impedance at high frequencies, as shown
starting value and sets a low-pass corner at 31 kHz for 5 k
sources. In applications where the source ground is not as
clean as would be desirable, a capacitor (illustrated as C7
on the evaluation board) from the VCAR input to the source
ground may prove beneficial. This capacitor is used in
addition to the grounded capacitor (illustrated as C2 on the
evaluation board) used in the feedback around the buffer,
assuming that the buffer is configured for gain.
00357-
024
NOTES
1. ADDITIONAL CIRCUIT DETAILS OMITTED
CX
1000pF
AUDIO +IN
(RS > 5k)
AUDIO +IN
SSM2166
C1
0.1F
7
FOR CLARITY.
Figure 25. Circuit Configuration for Use with High Impedance Signal Sources
The value of C7 should be the same as C6, which is the capacitor
value used between BUF OUT and VCAIN. This connection
makes the source ground noise appear as a common-mode signal
to the VCA, allowing the common-mode noise to be rejected by
the VCA differential input circuitry. C7 can also be useful in
reducing ground loop problems and in reducing noise coupling
from the power supply by balancing the impedances connected
to the inputs of the internal VCA.