參數(shù)資料
型號(hào): SSM1105
英文描述: NOT FOR NEW DESIGN: SCALAR SYSTEM MEMORY (SSM) FOR IMAGE PROCESSOR ICS
中文描述: 不適用于新設(shè)計(jì):標(biāo)量系統(tǒng)內(nèi)存部(SSM)的圖像處理器IC
文件頁數(shù): 1/4頁
文件大?。?/td> 82K
代理商: SSM1105
1/4
NOT FOR NEW DESIGN
November 2002
This is information on a product still in production but not recommended for new designs.
SSM1105V
Scalar System Memory (SSM)
for Image Processor ICs
FEATURES SUMMARY
I
System solution for use with image processing
scalar ICs
– For LCD monitors, projectors, and TVs
– Compatible with Pixelworks PW11x/PWx64
families (and similar image processors or mi-
cro-controllers)
I
Single integrated package, including:
– Dual bank Flash memories
– DDC, I
2
C, and PWM channels
– General purpose I/O
– Programmable logic
– In-System Programming via JTAG
I
Dual bank Flash memories
– Provide concurrent operation
– 5 Mbit main Flash memory
– 384 Kbit secondary Flash memory (divided
into 10 small sectors)
– Programmable Decode PLD for flexible ad-
dress mapping of both memories
I
Dual Display Data Channels (DDC)
– Supports DDC for both analog RGB and digi-
tal DVI video input channels
– DDC1/DDC2B VESA standard compliant
– 256 byte SRAM buffer for each DDC channel
I
Dual independent I
2
C channels
– Each capable of master or slave operation
– Control A/D converters, video decoders, and
future devices (tuner, audio, etc.)
I
Four Pulse Width Modulator (PWM) channels
– 16-bit resolution for period and for duty cycle
– 16-bit clock prescalers
I
Seven I/O ports with 52 I/O pins for Multifunction
I/O: GPIO, DDC, I
2
C, PWM, PLD I/O, and JTAG
I
3000 gate PLD with 16 macrocells, for creating
glue logic, state machines, clock dividers,
decoders, chip-selects, inverters; and to
prioritize interrupts from DDC, I
2
C, PWM
Figure 1. Packages
I
In-System Programming (ISP) with JTAG
– Program entire chip in 30-40 seconds with no
involvement of the processor
– Program with low-cost FlashLINK
I
Content Security: Programmable Security Bit
blocks access of device programmers / readers
I
Zero-Power Technology: memory and PLD
blocks automatically switch to stand-by current
between input changes
I
Package and Specifications
– 100-pin TQFP, 14 x 14mm
– 90 ns memory access time
– V
CC
Operating Voltage: 2.7V to 3.6V
TQFP100 (U)
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