
SSD1818A
Rev 1.2
P 11/47 Mar 2004
Solomon Systech
D
7
-D
0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D
7
is the MSB while D
0
is the
LSB.
When serial mode is selected, D
7
is the serial data input (SDA) and D
6
is the serial clock input (SCK).
V
DD
These pins are the Chip’s Power Supply pins. These pins are also act as the reference for the DC-DC
Converter output and the LCD driving voltages.
V
SS
These pins are the grounding of the chip. They are also act as the reference for the logic pins.
V
SS1
These pins are the inputs for internal DC-DC converter. The voltage of generated, V
EE
, equals to the
multiple factors times the potential different between these pins, V
SS1
, and V
DD
. The multiple factors, 2X,
3X, 4X or 5X are selected by different connections of the external capacitors. All voltage levels are
referenced to V
DD
.
Note: the potential of Vss
1
at this input pin must lower than or equal to V
SS
.
V
EE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the
internal DC-DC converter. The internal DC-DC converter is turned on when the
internal voltage booster
option is enabled. Please refer to the Set Power Control Register command for detail description.
When using internal DC-DC converter as voltage generator, voltage at this pin is used for internal
referencing only. It CANNOT be used for driving external circuitry.
C
1P
, C
1N
, C
2N
, C
2P
C
3N
and C
4N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these
pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or
5X. For detailed connections, please refer to the voltage converter section in the functional block
description.
V
L2
, V
L3
, V
L4
and V
L5
These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are
referenced to V
DD
. The voltage levels can be supplied externally or generated by the internal bias divider.
The bias divider is turned on when the output op-amp buffers are enabled. Please refer to the Set Power
Control Register command for detail description.
The voltage potential relationship of these pins are given as:
V
DD
> V
L2
> V
L3
> V
L4
> V
L5
> V
L6
In addition, assume the bias factor is known as a,
VL2 - VDD = 1/a * (VL6 - VDD)
VL3 - VDD = 2/a * (VL6 - VDD)
VL4 - VDD = (a-2)/a * (VL6 - VDD)
VL5 - VDD = (a-1)/a * (VL6 - VDD)
V
L6
This pin outputs the most negative LCD driving voltage level. The V
L6
can be supplied externally or
generated by the internal regulator.
Please refer to the Set Power Control Register command for detail
description.