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參數(shù)資料
| 型號(hào)： | SSD1818A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller |
| 中文描述： | LCD段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 642K |
| 代理商： | SSD1818A |
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Solomon Systech
Mar 2004
P 12/47 Rev 1.2
SSD1818A
M/
S
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected.
CL, M, MSTAT and DOF signals will be the output pins for slave devices.
When this pin is pulled low, slave mode is selected. CL, M, DOF are input pins getting signal from master
device. The state of MSTAT will be high impedance.
V
F
This pin is the input of the built-in voltage regulator for generating V
L6
. When external resistor network is
selected (IRS pulled low) to generate the LCD driving level, V
L6
, two external resistors should be added.
R
1
should be connected between V
DD
and V
F
. R
2
should be connected between V
F
and V
L6.
CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled.
The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external clock
source must be fed into the CL pin.
C68/
80
This pin is the MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is
selected. When the pin is pulled low, 8080 series interface is selected.
If Serial Interface is selected (P/S pulled low), the setting of this pin is ignored. The C68
/
80
pin must be
connected to a known logic state (either high or low).
P/
S
This pin is the serial/parallel interface selection input. When this pin is pulled high, parallel interface mode
is selected. When this pin is pulled low, serial interface will be selected.
Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/
W
(
WR
), E/(
RD
) are recommended to connect to
Vss.
Note2: Read back operation is only available in parallel mode.
C1, C0
These pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether
there are four chip modes. Please see the following list for reference.
C1
C0
Chip Mode
0
0
48 MUX Mode
0
1
54 MUX Mode
1
0
32 MUX Mode
1
1
64 MUX Mode
IRS
This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is
pulled high, the internal feedback resistors of the internal regulator for generating V
L6
will be enabled.
When it is pulled low, external resistors, R
1
should be connected to V
DD
and V
F
. R
2
should be connected
between V
F
and V
L6
, respectively.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSD1818ATR1 | LCD Segment / Common Driver with Controller |
| SSD1818AZ | LCD Segment / Common Driver with Controller |
| SSD1828Z | MOTOR LINEAR ACT 12VDC UNIPOLAR |
| SSD1828 | LCD Segment / Common Driver with Controller CMOS |
| SSD1852 | LCD Segment / Common Driver With Controller CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1818ATR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1818AZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1818Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1820A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1820ATR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
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