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參數(shù)資料
| 型號： | SSD1332U1R1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 的OLED /短差段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 367K |
| 代理商： | SSD1332U1R1 |
SOLOMON
Rev 0.23
08/2003
SSD1332
10
MPU Parallel 6800-series Interface
The parallel interface consists of 16 bi-directional data pins (D
0
-D
15
), R/W#(WR#), D/C#, E (RD#) and
CS#. R/W#(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM)
or the status register. RW#/(WR#) input Low indicates a write operation to Display Data RAM or Internal
Command Registers depending on the status of D/C# input. The E(RD#) input serves as data latch signal
(clock) when high provided that CS# is low and high respectively. Refer to Figure 5 of parallel timing
characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 4 below.
n+2
n+1
Write column
address
Dummy read
Data read1
R/
W#(WR#)
Data bus
N
n
E(RD#)
Data read2
Data read3
Figure 4 - Display data read back procedure - insertion of dummy read
MPU Parallel 8080-series Interface
The parallel interface consists of 16 bi-directional data pins (D
0
-D15), E (RD#), R/W#(WR#), D/C# and
CS#. The E(RD#) input serves as data read latch signal (clock) when low, provided that CS# is low and
high respectively. Display data or status register read is controlled by D/C#.
R/W#(WR#) input serves as data write latch signal (clock) when high provided that CS# is low and high
respectively. Display data or command register write is controlled by D/C#. Refer to Figure 6 of parallel
timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to
6800-series interface, a dummy read is also required before the first actual display data read.
MPU Serial Interface
The serial interface consists of serial clock SCK, serial data SDA, D/C# and CS#. SDA is shifted into an
8-bit shift register on every rising edge of SCL in the order of D
7
, D
6
, ... D
0
. D/C# is sampled on every
eighth clock and the data byte in the shift register is written to the Display Data RAM or command register
in the same clock.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
96 x 64 x 16bits.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display.
Current Control and Voltage Control
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