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參數(shù)資料
| 型號： | SSCP485PL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SSC P485 PL Transceiver IC |
| 中文描述： | 南南合作P485特等收發(fā)芯片 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大小： | 109K |
| 代理商： | SSCP485PL |
SSC P485 PL Transceiver IC
July 1998
3
Revision 5
24000828
ADVANCE INFORMATION
SSC P485 Pin Assignments
Pin
1
2
3
4
Mnemonic
4MHZ
NC
VSS
D
XIN
Name
Description
4 MHz Clock Out
No Connect
Digital Ground
Crystal Input
4 MHz clock output available for host microcontroller.
Digital ground reference.
Connected to external crystal to excite the IC’s internal
oscillator and digital clock.
Connected to external crystal to excite the IC’s internal
oscillator and digital clock.
5.0 VDC
±
10% digital supply voltage with respect to
VSS
D
.
Digital output, active high. Logic 1 state indicates 10 bit
times of idle line, logic 0 indicates detection of carrier or
non-idle line.
Digital input. After the preamble, a low on DI (SPACE)
transmits a superior2 state on SO, a high on DI (MARK)
transmits a superior1 state on SO.
Digital output. After the preamble and assuming
standard polarity: if superior1 state is detected on SI,
RO will be high (MARK), if superior2 state is detected
on SI, RO will be low (SPACE).
Digital input. Logic 1 (default, internal pullup) selects
10-bit frame (START, eight data bits, STOP), logic 0
selects 11-bit frame (START, nine data bits, STOP).
Active low digital output. Enables the external output
amplifier when driven high. Tri-states the external
output amplifier when driven low.
Active low digital input. RST* asynchronously forces
RO and ILD outputs to a high state and TS* to a low
state. RST* can be asserted anytime during normal
operation to force the reset state. RST* must be active
(low) for 1
μ
sec after VDD
D
and VDD
A
stabilize and the
crystal oscillator stabilizes to guarantee the internal
reset state. See Figure 10.
Analog ground reference.
Analog signal output. Tri-state enabled with internal
signal.
Connection for 680pF capacitor to ground.
Connection for 680pF capacitor to ground.
Analog signal input.
5.0 VDC
±
10% analog supply voltage with respect to
VSS
A
.
Reserved pin for testing.
Digital ground reference.
5
XOUT
Crystal Output
6
VDD
D
Digital Supply
7
ILD
Idle Line Detect
8
DI
Driver Input
9
RO
Receiver Output
10
WL
Word Length
11
TS*
Tristate
12
RST*
Reset
13
14
VSS
A
SO
Analog Ground
Signal Output
15
16
17
18
C2
C1
SI
VDD
A
Capacitor 2
Capacitor 1
Signal Input
Analog Supply
19
20
TP0
VSS
D
Test Point 0
Digital Ground
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