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參數(shù)資料
| 型號(hào)： | SRM4010 |
| 英文描述： | DC:DC Converter |
| 中文描述： | 直流：DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 224K |
| 代理商： | SRM4010 |
Microsemi
Colorado Division
800 Hoyt Street, Broomfield, CO. 80020, 303-469-2161, Fax: 303-466-3775
Page 7
Copyright 2000
2003-02-05 Rev. IR
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SRM4010
40A Synchronous Rectifier Module
COLOR ADO DIVISION
In applications where the peak transformer voltage is below the
minimum 7.5 volts needed to provide proper regulator input
voltage, power can be supplied to the regulator input from an
additional secondary winding through a diode. The peak voltage
fed to the REG
IN
pin should be below the absolute maximum
voltage of 20 volts. Voltages this high are undesirable however
since there is a power loss associated with the voltage drop in the
regulator.
Converter Switching Frequency
The converter switching frequency can range from 200 KHz to
400 KHz. From a SRM4010 module standpoint, there are limits
on the maximum ON time and maximum OFF time. This is due
to internal timing used for prediction. The timing circuitry will
saturate at low frequency if the times exceed the capability of
the timing circuits. At the high frequency end, the same timing is
less accurate
External Control Pins
There are 3 external control pins for tailoring the module
operation to the characteristics of the power converter. These
external pins provide maximum flexibility in using the module
in converter with different characteristics
SPD- Module Pin 9
This is used to tailor the module’s ability to differentiate between
valid turn on of the Catch diode and ringing that can occur at
light load. This pin is normally open, which sets the boundary for
normal turn on at 50nS for the drain voltage to fall from 4.3 volts
to 1.7 volts. In the open case, fall times between the thresholds
that are faster than 50nS are interpreted as valid turn ON’s caused
by the primary being switched off. Transitions slower than 50nS
are interpreted as ringing, which occurs in light load
discontinuous operation. In the light load case, the Catch
MOSFET is not turned on.. The speed of this threshold can be
changed by biasing pin 9. If the controller is not sensing normal
turn off from the primary, biasing this pin to ground through a
resistor can make the controller respond to slower transitions. If
the controller is responding falsely to ringing in a discontinuous
mode or skip cycle operation, the controller can be made to reject
faster ringing by biasing this pin to the +5V control power.
CPDT- Module Pin 8
This pin is used for an external capacitor to tailor the prediction
time for the Catch synchronous rectifier. The external capacitor
connects between pin 8 and SGND. This is the time between the
rise of the Catch Drain voltage and the rise of the Catch Gate
voltage. Typical values of this capacitor are 0 to 47 pF.
Increasing the capacitance increases the prediction time delay.
This time should be made as short as possible without causing
frequent reductions in the enhancement time due to converter
pulse width jitter. It is often useful to start with about 22 pF of
capacitance on pin 8 for initial debug. This can later be reduced
for more optimal efficiency after the converter is working.
CDLY- Module Pin 7
This pin is used to ensure that the transformer can be reset
during light load operation. To allow reset, the forward drive is
inhibited for a time from the turn on of the Catch MOSFET
Gate. A capacitor to ground sets the time duration where the
forward MOSFET Gate drive is disabled. Increasing the
capacitor increases the hold off time. The proper value of this
capacitor is a function of the amount of time needed to ensure
the transformer is reset. If the time is made too long, it inhibits
enhancement of the forward MOSFET during times when it is
carrying load current. If the time is made too short, there is a
problem with allowing the power transformer to reset properly
during light load operation.
T
H
P
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